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gpu: nvgpu: gp10b: Enable CILP mode for compute

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Allow enabling CILP for compute. Set CTA by default.

Bug 1517461

Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/661298
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Terje Bergstrom
2014-12-09 10:49:08 +02:00
committed by Deepak Nibade
parent d40f3fb273
commit 4493b6b200
3 changed files with 35 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -510,13 +510,14 @@ static int gr_gp10b_init_ctx_state(struct gk20a *g)
int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
u32 class,
u32 flags)
{
int err;
gk20a_dbg_fn("");
err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, flags);
err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags);
if (err)
return err;
@@ -566,9 +567,15 @@ int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
goto fail_free_betacb;
}
(*gr_ctx)->t18x.preempt_mode = flags;
(*gr_ctx)->preempt_mode = flags;
}
if (class == PASCAL_COMPUTE_A)
if (flags == NVGPU_GR_PREEMPTION_MODE_CILP)
(*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP;
else
(*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA;
gk20a_dbg_fn("done");
return err;
@@ -610,16 +617,24 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
u32 gfxp_preempt_option =
ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f();
u32 cilp_preempt_option =
ctxsw_prog_main_image_compute_preemption_options_control_cilp_f();
int err;
gk20a_dbg_fn("");
if (gr_ctx->t18x.preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) {
if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) {
gk20a_dbg_info("GfxP: %x", gfxp_preempt_option);
gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0,
gfxp_preempt_option);
}
if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_CILP) {
gk20a_dbg_info("CILP: %x", cilp_preempt_option);
gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0,
cilp_preempt_option);
}
if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) {
u32 addr;
u32 size;

3
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -39,14 +39,13 @@ struct gr_t18x {
};
struct gr_ctx_desc_t18x {
int preempt_mode;
struct mem_desc preempt_ctxsw_buffer;
struct mem_desc spill_ctxsw_buffer;
struct mem_desc betacb_ctxsw_buffer;
struct mem_desc pagepool_ctxsw_buffer;
};
#define NVGPU_GR_PREEMPTION_MODE_WFI 0
#define NVGPU_GR_PREEMPTION_MODE_GFXP 1
#define NVGPU_GR_PREEMPTION_MODE_CILP 3
#endif

16
drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h
View File

@@ -254,4 +254,20 @@ static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
{
return 0x00000068;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
{
return 0x00000084;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
{
return (v & 0x3) << 0;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
{
return 0x1;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
{
return 0x2;
}
#endif