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gpu: nvgpu: compile out non fusa LTC functionality

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nvgpu_ltc_sync_enabled functionality is used only in the kernel mode
submit path and for debugging. en_illegal_compstat functionality is
used for debugging .

Compile them out under CONFIG_NVGPU_NON_FUSA.

JIRA NVGPU-6982

Change-Id: I404d4b74b2e60ba4c2173ba0bfb643b1ecb6ba7c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2605011
(cherry picked from commit f4bcafe73c8f7184b5e125e3ff6e55ceccaf87eb)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2632547
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2021-10-04 11:42:36 +05:30
committed by mobile promotions
parent 2c560dce0e
commit 449a4823d4
21 changed files with 145 additions and 80 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/common/ltc/ltc.c
View File

@@ -48,16 +48,17 @@ int nvgpu_init_ltc_support(struct gk20a *g)
nvgpu_log_fn(g, " ");
g->mm.ltc_enabled_current = true;
g->mm.ltc_enabled_target = true;
if (ltc == NULL) {
ltc = nvgpu_kzalloc(g, sizeof(*ltc));
if (ltc == NULL) {
return -ENOMEM;
}
g->ltc = ltc;
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
nvgpu_spinlock_init(&g->ltc->ltc_enabled_lock);
g->mm.ltc_enabled_current = true;
g->mm.ltc_enabled_target = true;
#endif
}
if (g->ops.ltc.init_fs_state != NULL) {
@@ -86,6 +87,7 @@ int nvgpu_init_ltc_support(struct gk20a *g)
return 0;
}
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
void nvgpu_ltc_sync_enabled(struct gk20a *g)
{
if (g->ops.ltc.set_enabled == NULL) {
@@ -99,6 +101,7 @@ void nvgpu_ltc_sync_enabled(struct gk20a *g)
}
nvgpu_spinlock_release(&g->ltc->ltc_enabled_lock);
}
#endif
u32 nvgpu_ltc_get_ltc_count(struct gk20a *g)
{

4
drivers/gpu/nvgpu/hal/init/hal_ga100.c
View File

@@ -368,7 +368,9 @@ static const struct gops_ecc ga100_ops_ecc = {
static const struct gops_ltc_intr ga100_ops_ltc_intr = {
.configure = ga10b_ltc_intr_configure,
.isr = ga10b_ltc_intr_isr,
#ifdef CONFIG_NVGPU_NON_FUSA
.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
#endif
};
static const struct gops_ltc ga100_ops_ltc = {
@@ -379,7 +381,9 @@ static const struct gops_ltc ga100_ops_ltc = {
.init_fs_state = ga10b_ltc_init_fs_state,
.ltc_lts_set_mgmt_setup = ga10b_ltc_lts_set_mgmt_setup,
.flush = gm20b_flush_ltc,
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
.set_enabled = gp10b_ltc_set_enabled,
#endif
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,

4
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -337,7 +337,9 @@ static const struct gops_ltc_intr ga10b_ops_ltc_intr = {
.isr = ga10b_ltc_intr_isr,
.isr_extra = ga10b_ltc_intr_handle_lts_intr3_extra,
.ltc_intr3_configure_extra = ga10b_ltc_intr3_configure_extra,
#ifdef CONFIG_NVGPU_NON_FUSA
.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
#endif
};
static const struct gops_ltc ga10b_ops_ltc = {
@@ -348,7 +350,9 @@ static const struct gops_ltc ga10b_ops_ltc = {
.init_fs_state = ga10b_ltc_init_fs_state,
.ltc_lts_set_mgmt_setup = ga10b_ltc_lts_set_mgmt_setup,
.flush = gm20b_flush_ltc,
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
.set_enabled = gp10b_ltc_set_enabled,
#endif
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zbc_s_entry = ga10b_ltc_set_zbc_stencil_entry,
.set_zbc_color_entry = ga10b_ltc_set_zbc_color_entry,

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -149,7 +149,9 @@ static const struct gops_bios gm20b_ops_bios = {
static const struct gops_ltc_intr gm20b_ops_ltc_intr = {
.configure = gm20b_ltc_intr_configure,
.isr = gm20b_ltc_intr_isr,
#ifdef CONFIG_NVGPU_NON_FUSA
.en_illegal_compstat = NULL,
#endif
};
static const struct gops_ltc gm20b_ops_ltc = {
@@ -159,6 +161,8 @@ static const struct gops_ltc gm20b_ops_ltc = {
#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
.determine_L2_size_bytes = gm20b_determine_L2_size_bytes,
.init_fs_state = gm20b_ltc_init_fs_state,
#endif
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
.set_enabled = gm20b_ltc_set_enabled,
#endif
#ifdef CONFIG_NVGPU_GRAPHICS

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -264,7 +264,9 @@ static const struct gops_ecc gv11b_ops_ecc = {
static const struct gops_ltc_intr gv11b_ops_ltc_intr = {
.configure = gv11b_ltc_intr_configure,
.isr = gv11b_ltc_intr_isr,
#ifdef CONFIG_NVGPU_NON_FUSA
.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
#endif
};
static const struct gops_ltc gv11b_ops_ltc = {
@@ -274,7 +276,9 @@ static const struct gops_ltc gv11b_ops_ltc = {
.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
.init_fs_state = gv11b_ltc_init_fs_state,
.flush = gm20b_flush_ltc,
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
.set_enabled = gp10b_ltc_set_enabled,
#endif
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -308,7 +308,9 @@ static const struct gops_ecc tu104_ops_ecc = {
static const struct gops_ltc_intr tu104_ops_ltc_intr = {
.configure = gv11b_ltc_intr_configure,
.isr = gv11b_ltc_intr_isr,
#ifdef CONFIG_NVGPU_NON_FUSA
.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
#endif
};
static const struct gops_ltc tu104_ops_ltc = {
@@ -318,7 +320,9 @@ static const struct gops_ltc tu104_ops_ltc = {
.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
.init_fs_state = ltc_tu104_init_fs_state,
.flush = gm20b_flush_ltc,
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
.set_enabled = gp10b_ltc_set_enabled,
#endif
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,

4
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GA10B LTC INTR
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -95,6 +95,7 @@ static void ga10b_ltc_intr1_configure(struct gk20a *g)
/* Read back register for write synchronization */
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
#ifdef CONFIG_NVGPU_NON_FUSA
/* illegal_compstat interrupts can be also controlled through
* debug_fs, so enable/disable based on g->ltc_intr_en_illegal_compstat
* settings
@@ -103,6 +104,7 @@ static void ga10b_ltc_intr1_configure(struct gk20a *g)
g->ops.ltc.intr.en_illegal_compstat(g,
g->ltc_intr_en_illegal_compstat);
}
#endif
}
/* LTC interrupts included in intr2 are not used for ga10b */

4
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.h
View File

@@ -1,7 +1,7 @@
/*
* GV11B L2 INTR
*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,7 +31,9 @@ struct gk20a;
void gv11b_ltc_intr_configure(struct gk20a *g);
void gv11b_ltc_intr_isr(struct gk20a *g, u32 ltc);
#ifdef CONFIG_NVGPU_NON_FUSA
void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable);
#endif
void gv11b_ltc_intr_init_counters(struct gk20a *g,
u32 corrected_delta, u32 corrected_overflow,

6
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c
View File

@@ -38,12 +38,13 @@ void gv11b_ltc_intr_configure(struct gk20a *g)
{
u32 reg;
/* Disable ltc interrupts to reduce nosie and increase perf */
/* Disable ltc interrupts to reduce noise and increase perf */
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m();
reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m();
nvgpu_writel(g, ltc_ltcs_ltss_intr_r(), reg);
#ifdef CONFIG_NVGPU_NON_FUSA
/* illegal_compstat interrupts can be also controlled through
* debug_fs, so enable/disable based on g->ltc_intr_en_illegal_compstat
* settings
@@ -52,6 +53,7 @@ void gv11b_ltc_intr_configure(struct gk20a *g)
g->ops.ltc.intr.en_illegal_compstat(g,
g->ltc_intr_en_illegal_compstat);
}
#endif
/* Enable ECC interrupts */
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
@@ -60,6 +62,7 @@ void gv11b_ltc_intr_configure(struct gk20a *g)
nvgpu_writel(g, ltc_ltcs_ltss_intr_r(), reg);
}
#ifdef CONFIG_NVGPU_NON_FUSA
void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable)
{
u32 val;
@@ -77,6 +80,7 @@ void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable)
}
nvgpu_writel(g, ltc_ltcs_ltss_intr_r(), val);
}
#endif
void gv11b_ltc_intr_init_counters(struct gk20a *g,
u32 corrected_delta, u32 corrected_overflow,

4
drivers/gpu/nvgpu/hal/ltc/ltc_gp10b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GP10B L2
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -58,6 +58,7 @@ u64 gp10b_determine_L2_size_bytes(struct gk20a *g)
return ret;
}
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled)
{
u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
@@ -73,3 +74,4 @@ void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled)
nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
}
#endif

2
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
View File

@@ -234,7 +234,9 @@ static const struct gops_ltc vgpu_ga10b_ops_ltc = {
.determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
.init_fs_state = vgpu_ltc_init_fs_state,
.flush = NULL,
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
.set_enabled = NULL,
#endif
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zbc_s_entry = NULL,
.set_zbc_color_entry = NULL,

4
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
View File

@@ -198,7 +198,9 @@ static const struct gops_bios vgpu_gv11b_ops_bios = {
static const struct gops_ltc_intr vgpu_gv11b_ops_ltc_intr = {
.configure = NULL,
.isr = NULL,
#ifdef CONFIG_NVGPU_NON_FUSA
.en_illegal_compstat = NULL,
#endif
};
static const struct gops_ltc vgpu_gv11b_ops_ltc = {
@@ -207,7 +209,9 @@ static const struct gops_ltc vgpu_gv11b_ops_ltc = {
.determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
.init_fs_state = vgpu_ltc_init_fs_state,
.flush = NULL,
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
.set_enabled = NULL,
#endif
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zbc_s_entry = NULL,
.set_zbc_color_entry = NULL,

3
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -761,7 +761,10 @@ struct gk20a {
struct nvgpu_ce_app *ce_app;
#ifdef CONFIG_NVGPU_NON_FUSA
/** Flag to control enabling/disabling of illegal compstat intr. */
bool ltc_intr_en_illegal_compstat;
#endif
/** @endcond */
/** Are we currently running on a FUSA device configuration? */

4
drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
View File

@@ -51,7 +51,9 @@ struct gops_ltc_intr {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
void (*configure)(struct gk20a *g);
#ifdef CONFIG_NVGPU_NON_FUSA
void (*en_illegal_compstat)(struct gk20a *g, bool enable);
#endif
void (*isr_extra)(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
void (*ltc_intr3_configure_extra)(struct gk20a *g, u32 *reg);
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
@@ -134,7 +136,9 @@ struct gops_ltc {
int (*ecc_init)(struct gk20a *g);
void (*init_fs_state)(struct gk20a *g);
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
void (*set_enabled)(struct gk20a *g, bool enabled);
#endif
void (*ltc_lts_set_mgmt_setup)(struct gk20a *g);
#ifdef CONFIG_NVGPU_GRAPHICS
void (*set_zbc_color_entry)(struct gk20a *g,

36
drivers/gpu/nvgpu/include/nvgpu/ltc.h
View File

@@ -39,10 +39,12 @@ struct nvgpu_ecc_stat;
* This structure stores data related to ltc unit.
*/
struct nvgpu_ltc {
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
/**
* Spinlock to protect all ltc operations.
*/
struct nvgpu_spinlock ltc_enabled_lock;
#endif
/** Maximum ltc count value is read from h/w top config register. */
u32 max_ltc_count;
/** Enumerated ltc count value is read from h/w priv ring register. */
@@ -116,22 +118,6 @@ int nvgpu_init_ltc_support(struct gk20a *g);
* LTC unit data will be no longer accessible by s/w.
*/
void nvgpu_ltc_remove_support(struct gk20a *g);
/**
* @brief Enable/Disable caching feature of L2.
*
* @param g [in] Pointer to GPU driver struct.
*
* This function will enable/disable caching feature of L2 based on
* #mm.ltc_enabled_target. With #mm.ltc_enabled_target set to true,
* gpu l2 caching feature will be enabled. Gpu L2 caching is enabled with h/w
* power-on and can only be changed after h/w reset, before the first
* transaction received by L2.
* With #mm.ltc_enabled_target set to false, Gpu L2 caching will be disabled.
* With Gpu L2 cache disabled, all transactions will miss in L2 and data will
* be always write-through to main memory.
*
*/
void nvgpu_ltc_sync_enabled(struct gk20a *g);
/**
* @brief Get enumerated ltcs count.
*
@@ -169,4 +155,22 @@ u32 nvgpu_ltc_get_slices_per_ltc(struct gk20a *g);
*/
u32 nvgpu_ltc_get_cacheline_size(struct gk20a *g);
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
/**
* @brief Enable/Disable caching feature of L2.
*
* @param g [in] Pointer to GPU driver struct.
*
* This function will enable/disable caching feature of L2 based on
* #mm.ltc_enabled_target. With #mm.ltc_enabled_target set to true,
* gpu l2 caching feature will be enabled. Gpu L2 caching is enabled with h/w
* power-on and can only be changed after h/w reset, before the first
* transaction received by L2.
* With #mm.ltc_enabled_target set to false, Gpu L2 caching will be disabled.
* With Gpu L2 cache disabled, all transactions will miss in L2 and data will
* be always write-through to main memory.
*
*/
void nvgpu_ltc_sync_enabled(struct gk20a *g);
#endif
#endif /* NVGPU_LTC_H */

4
drivers/gpu/nvgpu/include/nvgpu/mm.h
View File

@@ -357,10 +357,14 @@ struct mm_gk20a {
int physical_bits;
/** True if whole comptag memory is used for compress rendering. */
bool use_full_comp_tag_line;
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
/** True if LTC sw setup is ready. */
bool ltc_enabled_current;
/** True if LTC hw setup is ready. */
bool ltc_enabled_target;
#endif
/** Disable big page support. */
bool disable_bigpage;

1
libs/dgpu/libnvgpu-drv-dgpu_safe.export
View File

@@ -526,7 +526,6 @@ nvgpu_ltc_get_cacheline_size
nvgpu_ltc_get_ltc_count
nvgpu_ltc_get_slices_per_ltc
nvgpu_ltc_remove_support
nvgpu_ltc_sync_enabled
nvgpu_local_golden_image_get_fault_injection
nvgpu_log_msg_impl
nvgpu_cic_mon_intr_mask

1
libs/igpu/libnvgpu-drv-igpu_safe.export
View File

@@ -543,7 +543,6 @@ nvgpu_ltc_get_cacheline_size
nvgpu_ltc_get_ltc_count
nvgpu_ltc_get_slices_per_ltc
nvgpu_ltc_remove_support
nvgpu_ltc_sync_enabled
nvgpu_local_golden_image_get_fault_injection
nvgpu_log_msg_impl
nvgpu_cic_mon_intr_mask

2
userspace/required_tests.ini
View File

@@ -431,10 +431,8 @@ test_ltc_functionality_tests.ltc_functionality_tests=0
test_ltc_init_support.ltc_init_support=0
test_ltc_intr.ltc_intr=0
test_ltc_intr_configure.ltc_intr_configure=0
test_ltc_intr_en_illegal_compstat.ltc_intr_en_illegal_compstat=0
test_ltc_negative_tests.ltc_negative_tests=0
test_ltc_remove_support.ltc_remove_support=0
test_ltc_set_enabled.ltc_set_enabled=0
[nvgpu-netlist]
test_netlist_init_support.netlist_init_support=0

66
userspace/units/ltc/nvgpu-ltc.c
View File

@@ -385,8 +385,10 @@ int test_ltc_functionality_tests(struct unit_module *m,
u32 slice_per_ltc;
u32 cacheline_size;
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
g->mm.ltc_enabled_current = false;
nvgpu_ltc_sync_enabled(g);
#endif
ltc_count = nvgpu_ltc_get_ltc_count(g);
if (ltc_count != NUM_LTC) {
@@ -409,10 +411,13 @@ int test_ltc_negative_tests(struct unit_module *m,
{
int err = 0;
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
g->mm.ltc_enabled_current = g->mm.ltc_enabled_target;
nvgpu_ltc_sync_enabled(g);
g->ops.ltc.set_enabled = NULL;
nvgpu_ltc_sync_enabled(g);
#endif
g->ops.ltc.ltc_remove_support(g);
g->ops.ltc.ltc_remove_support(g);
err = g->ops.ltc.init_ltc_support(g);
@@ -564,34 +569,13 @@ done:
return err;
}
int test_ltc_intr_en_illegal_compstat(struct unit_module *m,
struct gk20a *g, void *args)
{
u32 val;
/* clear the reg to be sure */
nvgpu_posix_io_writel_reg_space(g, ltc_ltcs_ltss_intr_r(), 0);
g->ops.ltc.intr.en_illegal_compstat(g, true);
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
if ((val & ltc_ltcs_ltss_intr_en_illegal_compstat_m()) == 0) {
unit_return_fail(m, "failed to enable illegal compstat\n");
}
g->ops.ltc.intr.en_illegal_compstat(g, false);
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
if ((val & ltc_ltcs_ltss_intr_en_illegal_compstat_m()) != 0) {
unit_return_fail(m, "failed to disable illegal compstat\n");
}
return UNIT_SUCCESS;
}
int test_ltc_intr_configure(struct unit_module *m,
struct gk20a *g, void *args)
{
u32 val;
#ifdef CONFIG_NVGPU_NON_FUSA
void (*save_func)(struct gk20a *g, bool en);
#endif
g->ops.ltc.intr.configure(g);
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
@@ -602,9 +586,11 @@ int test_ltc_intr_configure(struct unit_module *m,
unit_return_fail(m, "failed to configure intr\n");
}
#ifdef CONFIG_NVGPU_NON_FUSA
/* for branch coverage test case where this HAL isn't configured */
save_func = g->ops.ltc.intr.en_illegal_compstat;
g->ops.ltc.intr.en_illegal_compstat = NULL;
#endif
g->ops.ltc.intr.configure(g);
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
if ((val & (ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
@@ -613,7 +599,10 @@ int test_ltc_intr_configure(struct unit_module *m,
ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f())) {
unit_return_fail(m, "failed to configure intr\n");
}
#ifdef CONFIG_NVGPU_NON_FUSA
g->ops.ltc.intr.en_illegal_compstat = save_func;
#endif
return UNIT_SUCCESS;
}
@@ -638,6 +627,30 @@ int test_determine_L2_size_bytes(struct unit_module *m,
return UNIT_SUCCESS;
}
#ifdef CONFIG_NVGPU_NON_FUSA
int test_ltc_intr_en_illegal_compstat(struct unit_module *m,
struct gk20a *g, void *args)
{
u32 val;
/* clear the reg to be sure */
nvgpu_posix_io_writel_reg_space(g, ltc_ltcs_ltss_intr_r(), 0);
g->ops.ltc.intr.en_illegal_compstat(g, true);
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
if ((val & ltc_ltcs_ltss_intr_en_illegal_compstat_m()) == 0) {
unit_return_fail(m, "failed to enable illegal compstat\n");
}
g->ops.ltc.intr.en_illegal_compstat(g, false);
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
if ((val & ltc_ltcs_ltss_intr_en_illegal_compstat_m()) != 0) {
unit_return_fail(m, "failed to disable illegal compstat\n");
}
return UNIT_SUCCESS;
}
int test_ltc_set_enabled(struct unit_module *m, struct gk20a *g, void *args)
{
u32 val;
@@ -668,6 +681,7 @@ int test_ltc_set_enabled(struct unit_module *m, struct gk20a *g, void *args)
return UNIT_SUCCESS;
}
#endif
int test_flush_ltc(struct unit_module *m, struct gk20a *g, void *args)
{
@@ -711,11 +725,13 @@ struct unit_module_test nvgpu_ltc_tests[] = {
UNIT_TEST(ltc_functionality_tests, test_ltc_functionality_tests,
NULL, 0),
UNIT_TEST(ltc_intr, test_ltc_intr, NULL, 0),
UNIT_TEST(ltc_intr_en_illegal_compstat,
test_ltc_intr_en_illegal_compstat, NULL, 0),
UNIT_TEST(ltc_intr_configure, test_ltc_intr_configure, NULL, 0),
UNIT_TEST(ltc_determine_L2_size, test_determine_L2_size_bytes, NULL, 0),
#ifdef CONFIG_NVGPU_NON_FUSA
UNIT_TEST(ltc_intr_en_illegal_compstat,
test_ltc_intr_en_illegal_compstat, NULL, 0),
UNIT_TEST(ltc_set_enabled, test_ltc_set_enabled, NULL, 0),
#endif
UNIT_TEST(ltc_flush, test_flush_ltc, NULL, 0),
UNIT_TEST(ltc_negative_tests, test_ltc_negative_tests, NULL, 0),
UNIT_TEST(ltc_remove_support, test_ltc_remove_support, NULL, 0),

55
userspace/units/ltc/nvgpu-ltc.h
View File

@@ -108,14 +108,12 @@ int test_ltc_ecc_init_free(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: nvgpu_ltc_sync_enabled, nvgpu_ltc_get_ltc_count,
* Targets: nvgpu_ltc_get_ltc_count,
* nvgpu_ltc_get_slices_per_ltc, nvgpu_ltc_get_cacheline_size
*
* Input: None
*
* Steps:
* - Set ltc_enabled_current to false and then call
* nvgpu_ltc_sync_enabled.
* - Call nvgpu_ltc_get_ltc_count
* - Call nvgpu_ltc_get_slices_per_ltc
* - Call nvgpu_ltc_get_cacheline_size
@@ -133,14 +131,13 @@ int test_ltc_functionality_tests(struct unit_module *m,
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_ltc_sync_enabled, gops_ltc.ltc_remove_support,
* Targets: gops_ltc.ltc_remove_support,
* gops_ltc.init_ltc_support, nvgpu_init_ltc_support,
* nvgpu_ltc_remove_support
*
* Input: None
*
* Steps:
* - Set ltc.set_enabled to NULL and then call nvgpu_ltc_sync_enabled
* - Call gops_ltc.ltc_remove_support twice
* - Call gops_ltc.init_ltc_support
*
@@ -248,29 +245,6 @@ int test_ltc_remove_support(struct unit_module *m,
*/
int test_ltc_intr(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_ltc_intr_en_illegal_compstat
*
* Description: Validate the inter_en_illegal_compstat API.
*
* Test Type: Feature
*
* Targets: gops_ltc_intr.en_illegal_compstat, gv11b_ltc_intr_en_illegal_compstat
*
* Input: None
*
* Steps:
* - Clear the LTC intr register (NV_PLTCG_LTCS_LTSS_INTR).
* - Call the gv11b_ltc_intr_en_illegal_compstat HAL requesting enable.
* - Verify correct setting in LTC intr register.
* - Call the gv11b_ltc_intr_en_illegal_compstat HAL requesting disable.
* - Verify correct setting in LTC intr register.
*
* Output: Returns PASS if register is configured correctly. FAIL otherwise.
*/
int test_ltc_intr_en_illegal_compstat(struct unit_module *m,
struct gk20a *g, void *args);
/**
* Test specification for: test_ltc_intr_configure
*
@@ -316,6 +290,30 @@ int test_ltc_intr_configure(struct unit_module *m,
int test_determine_L2_size_bytes(struct unit_module *m,
struct gk20a *g, void *args);
#ifdef CONFIG_NVGPU_NON_FUSA
/**
* Test specification for: test_ltc_intr_en_illegal_compstat
*
* Description: Validate the inter_en_illegal_compstat API.
*
* Test Type: Feature
*
* Targets: gops_ltc_intr.en_illegal_compstat, gv11b_ltc_intr_en_illegal_compstat
*
* Input: None
*
* Steps:
* - Clear the LTC intr register (NV_PLTCG_LTCS_LTSS_INTR).
* - Call the gv11b_ltc_intr_en_illegal_compstat HAL requesting enable.
* - Verify correct setting in LTC intr register.
* - Call the gv11b_ltc_intr_en_illegal_compstat HAL requesting disable.
* - Verify correct setting in LTC intr register.
*
* Output: Returns PASS if register is configured correctly. FAIL otherwise.
*/
int test_ltc_intr_en_illegal_compstat(struct unit_module *m,
struct gk20a *g, void *args);
/**
* Test specification for: test_ltc_set_enabled
*
@@ -338,6 +336,7 @@ int test_determine_L2_size_bytes(struct unit_module *m,
* Output: Returns PASS if register is configured correctly. FAIL otherwise.
*/
int test_ltc_set_enabled(struct unit_module *m, struct gk20a *g, void *args);
#endif
/**
* Test specification for: test_flush_ltc