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gpu: nvgpu: ga10x: add missing LTC ECC related registers and fields
1. Registers NV_PLTCG_LTC0_LTS0_DSTG_ECC_REPORT and NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS are deprecated. Remove them. 2. Define NV_PLTCG_LTC0_LTS0_INTR3 for ga100. 3. Add fields and constants for the register NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS. 4. Add new fields for the register NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL. Bug 3446731 Change-Id: I3e41198b7b2e75ff69b5c6193e6fd54efae15752 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2633958 Reviewed-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
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Sagar Kamble
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@@ -284,11 +284,7 @@
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(0x8000000U)
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#define ltc_ltc0_lts0_intr_r() (0x0014040cU)
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#define ltc_ltc0_lts0_intr2_r() (0x00140408U)
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#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU)
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#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U)
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#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU)
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#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U)
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#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU)
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#define ltc_ltc0_lts0_intr3_r() (0x00140588U)
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#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U)
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#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
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#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U)
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@@ -321,9 +317,32 @@
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#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f() (0x0U)
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#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_enabled_f()\
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(0x20000000U)
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#define ltc_ltc0_lts0_dstg_ecc_address_r() (0x00140520U)
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#define ltc_ltc0_lts0_dstg_ecc_address_info_ram_m() (U32(0x1U) << 22U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_r() (0x001404fcU)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_v(r) (((r) >> 22U) & 0xffU)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram0_v()\
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(0x00000000U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram1_v()\
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(0x00000001U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram2_v()\
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(0x00000002U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram3_v()\
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(0x00000003U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram4_v()\
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(0x00000004U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram5_v()\
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(0x00000005U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram6_v()\
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(0x00000006U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram7_v()\
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(0x00000007U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank0_v() (0x00000008U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank1_v() (0x00000009U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank2_v() (0x0000000aU)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank3_v() (0x0000000bU)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_v(r) (((r) >> 30U) & 0x3U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_rstg_v() (0x00000000U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_tstg_v() (0x00000001U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_dstg_v() (0x00000002U)
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#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() (0x001404f4U)
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#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s() (16U)
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#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m()\
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@@ -336,6 +355,23 @@
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(U32(0xffffU) << 0U)
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#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(r)\
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(((r) >> 0U) & 0xffffU)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_r() (0x001404ecU)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_f(v)\
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((U32(v) & 0x1U) << 4U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_f(v)\
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((U32(v) & 0x1U) << 5U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_rstg_f(v)\
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((U32(v) & 0x1U) << 6U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_rstg_f(v)\
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((U32(v) & 0x1U) << 7U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_tstg_f(v)\
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((U32(v) & 0x1U) << 8U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_tstg_f(v)\
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((U32(v) & 0x1U) << 9U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_dstg_f(v)\
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((U32(v) & 0x1U) << 10U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_dstg_f(v)\
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((U32(v) & 0x1U) << 11U)
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#define ltc_ltc0_lts0_l2_cache_ecc_status_r() (0x001404f0U)
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#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()\
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(U32(0x1U) << 0U)
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@@ -345,9 +345,32 @@
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#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f() (0x0U)
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#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_enabled_f()\
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(0x20000000U)
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#define ltc_ltc0_lts0_dstg_ecc_address_r() (0x00140520U)
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#define ltc_ltc0_lts0_dstg_ecc_address_info_ram_m() (U32(0x1U) << 22U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_r() (0x001404fcU)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_v(r) (((r) >> 22U) & 0xffU)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram0_v()\
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(0x00000000U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram1_v()\
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(0x00000001U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram2_v()\
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(0x00000002U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram3_v()\
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(0x00000003U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram4_v()\
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(0x00000004U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram5_v()\
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(0x00000005U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram6_v()\
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(0x00000006U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_clrbe_trlram7_v()\
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(0x00000007U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank0_v() (0x00000008U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank1_v() (0x00000009U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank2_v() (0x0000000aU)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_ram_dstg_db_bank3_v() (0x0000000bU)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_v(r) (((r) >> 30U) & 0x3U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_rstg_v() (0x00000000U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_tstg_v() (0x00000001U)
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#define ltc_ltc0_lts0_l2_cache_ecc_address_subunit_dstg_v() (0x00000002U)
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#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() (0x001404f4U)
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#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s() (16U)
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#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(r)\
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@@ -356,6 +379,23 @@
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#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s() (16U)
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#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(r)\
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(((r) >> 0U) & 0xffffU)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_r() (0x001404ecU)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_f(v)\
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((U32(v) & 0x1U) << 4U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_f(v)\
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((U32(v) & 0x1U) << 5U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_rstg_f(v)\
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((U32(v) & 0x1U) << 6U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_rstg_f(v)\
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((U32(v) & 0x1U) << 7U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_tstg_f(v)\
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((U32(v) & 0x1U) << 8U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_tstg_f(v)\
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((U32(v) & 0x1U) << 9U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_corrected_err_dstg_f(v)\
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((U32(v) & 0x1U) << 10U)
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#define ltc_ltc0_lts0_l2_cache_ecc_control_inject_uncorrected_err_dstg_f(v)\
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((U32(v) & 0x1U) << 11U)
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#define ltc_ltc0_lts0_l2_cache_ecc_status_r() (0x001404f0U)
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#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()\
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(U32(0x1U) << 0U)
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