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gpu: nvgpu: add mc.reset_engine hal for nvgpu-next

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Engine reset process has changed for nvgpu-next. Add mc.reset_engine
gops for nvgpu-next.
Modify engine reset functions to use mc.reset_engine hal.

Jira NVGPU-5145

Change-Id: I176800212042eaef71c8cbd4bc499805c5af0e60
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2312485
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2020-03-13 14:21:43 -07:00
committed by Alex Waterman
parent a2080a1208
commit 44f12288ad
5 changed files with 72 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/nvgpu/common/ce/ce.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,14 +31,34 @@
int nvgpu_ce_init_support(struct gk20a *g)
{
u32 ce_reset_mask;
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
int err = 0;
#endif
if (g->ops.ce.set_pce2lce_mapping != NULL) {
g->ops.ce.set_pce2lce_mapping(g);
}
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (g->ops.mc.reset_engine != NULL) {
err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_GRCE);
if (err != 0) {
nvgpu_err(g, "NVGPU_ENGINE_GRCE reset failed");
return err;
}
err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_ASYNC_CE);
if (err != 0) {
nvgpu_err(g, "NVGPU_ENGINE_ASYNC_CE reset failed");
return err;
}
} else {
#endif
ce_reset_mask = nvgpu_engine_get_all_ce_reset_mask(g);
g->ops.mc.reset(g, ce_reset_mask);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
}
#endif
nvgpu_cg_slcg_ce2_load_enable(g);

14
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -630,7 +630,21 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
if ((engine_enum == NVGPU_ENGINE_GRCE) ||
(engine_enum == NVGPU_ENGINE_ASYNC_CE)) {
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
int err = 0;
if (g->ops.mc.reset_engine != NULL) {
err = g->ops.mc.reset_engine(g,
engine_info->nvgpu_next.reset_id);
if (err != 0) {
nvgpu_err(g, "failed to reset ce engine");
}
} else {
#endif
g->ops.mc.reset(g, engine_info->reset_mask);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
}
#endif
}
}
#endif

31
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -45,7 +45,7 @@
#include <nvgpu/mc.h>
#include <nvgpu/gops_mc.h>
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include "nvgpu/gr/nvgpu_next_gr.h"
#include <nvgpu/engines.h>
#endif
#include "gr_priv.h"
@@ -647,13 +647,34 @@ exit:
return err;
}
static void gr_init_prepare_hw(struct gk20a *g)
static int gr_init_prepare_hw(struct gk20a *g)
{
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
int err;
if (g->ops.mc.reset_engine != NULL) {
g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_GR);
if (err != 0) {
nvgpu_err(g, "NVGPU_ENGINE_GR reset failed");
return err;
}
err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_GRCE);
if (err != 0) {
nvgpu_err(g, "NVGPU_ENGINE_GRCE reset failed");
return err;
}
} else {
#endif
/* reset gr engine */
g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_GRAPH) |
g->ops.mc.reset_mask(g, NVGPU_UNIT_BLG) |
g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
}
#endif
nvgpu_cg_init_gr_load_gating_prod(g);
/* Disable elcg until it gets enabled later in the init*/
@@ -661,6 +682,7 @@ static void gr_init_prepare_hw(struct gk20a *g)
/* enable fifo access */
g->ops.gr.init.fifo_access(g, true);
return 0;
}
int nvgpu_gr_enable_hw(struct gk20a *g)
@@ -669,7 +691,10 @@ int nvgpu_gr_enable_hw(struct gk20a *g)
nvgpu_log_fn(g, " ");
gr_init_prepare_hw(g);
err = gr_init_prepare_hw(g);
if (err != 0) {
return err;
}
err = gr_init_reset_enable_hw(g);
if (err != 0) {

2
drivers/gpu/nvgpu/hal/rc/rc_gv11b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

9
drivers/gpu/nvgpu/include/nvgpu/gops_mc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,9 @@
#include <nvgpu/types.h>
#include <nvgpu/mc.h>
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu/engines.h>
#endif
/**
* @file
@@ -326,6 +329,10 @@ struct gops_mc {
*/
void (*ltc_isr)(struct gk20a *g);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include "include/nvgpu/nvgpu_next_gops_mc.h"
#endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
};