nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Don't query engine id for inval engine

Browse Source 
When we get a PBDMA MMU fault, we won't be able to map the MMU id
into an engine id for reset. We still pass FIFO_INVAL_ENGINE_ID to
gk20a_fifo_should_defer_engine_reset() which causes an unnecessary
debug spew.

Check for FIFO_INVAL_ENGINE before calling
gk20a_fifo_should_defer_engine_reset().

Change-Id: I6f4a49be194cbc6070c1a1c667059de2ea79790f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1321492
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-03-15 12:45:08 -07:00
committed by mobile promotions
parent 51f3f542fa
commit 467d0b1a19
1 changed files with 18 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1566,21 +1566,25 @@ static bool gk20a_fifo_handle_mmu_fault(
tsg = &g->fifo.tsg[ch->tsgid];
/* check if engine reset should be deferred */
if ((ch || tsg) && gk20a_fifo_should_defer_engine_reset(g,
engine_id, f.engine_subid_v, fake_fault)) {
g->fifo.deferred_fault_engines |= BIT(engine_id);
if (engine_id != FIFO_INVAL_ENGINE_ID) {
bool defer = gk20a_fifo_should_defer_engine_reset(g,
engine_id, f.engine_subid_v,
fake_fault);
if ((ch || tsg) && defer) {
g->fifo.deferred_fault_engines |= BIT(engine_id);
/* handled during channel free */
g->fifo.deferred_reset_pending = true;
gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg,
"sm debugger attached,"
" deferring channel recovery to channel free");
} else if (engine_id != FIFO_INVAL_ENGINE_ID) {
/* if lock is already taken, a reset is taking place
so no need to repeat */
if (nvgpu_mutex_tryacquire(&g->fifo.gr_reset_mutex)) {
gk20a_fifo_reset_engine(g, engine_id);
nvgpu_mutex_release(&g->fifo.gr_reset_mutex);
/* handled during channel free */
g->fifo.deferred_reset_pending = true;
gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg,
"sm debugger attached,"
" deferring channel recovery to channel free");
} else {
/* if lock is already taken, a reset is taking place
so no need to repeat */
if (nvgpu_mutex_tryacquire(&g->fifo.gr_reset_mutex)) {
gk20a_fifo_reset_engine(g, engine_id);
nvgpu_mutex_release(&g->fifo.gr_reset_mutex);
}
}
}