gpu: nvgpu: unit: update cg unit test

CG unit tests check for invalid registers access during configuration
of various CG modes for various units that involve multiple registers
accesses. Since ECC detect is now being done in hal init now,
corresponding registers need to be added to io space.

Bug 2919887

Change-Id: I8ded6a95952d810d9c8627a71752266e493e2c47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332262
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Prateek sethi
2020-04-16 22:05:29 +05:30
committed by Alex Waterman
parent 091e4b9396
commit 470fe3a6d4
2 changed files with 42 additions and 1 deletions

View File

@@ -32,6 +32,10 @@
#include <nvgpu/fifo/userd.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/posix/io.h>
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
#include "hal/init/hal_gv11b.h"
#include "nvgpu-fifo-common.h"
@@ -138,6 +142,18 @@ int test_fifo_init_support(struct unit_module *m, struct gk20a *g, void *args)
goto fail;
}
if (nvgpu_posix_io_add_reg_space(g,
gr_fecs_feature_override_ecc_r(), 0x4) != 0) {
unit_err(m, "Add reg space failed!\n");
return UNIT_FAIL;
}
if (nvgpu_posix_io_add_reg_space(g,
gr_fecs_feature_override_ecc_1_r(), 0x4) != 0) {
unit_err(m, "Add reg space failed!\n");
return UNIT_FAIL;
}
gv11b_init_hal(g);
g->ops.gr.init.get_no_of_sm = stub_gv11b_gr_init_get_no_of_sm;