gpu: nvgpu: pmuif: Fix MISRA Rule 21.2 violations

MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations caused by include guards in pmuif by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H'. JIRA NVGPU-1028 Change-Id: I19471ed8d8f7b278f497df74f760cdb1edc43ed0 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808133 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2025-12-24 02:22:34 +03:00 · 2018-08-28 14:21:33 +05:30
parent f18f06f104
commit 471be33718
19 changed files with 68 additions and 68 deletions
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef __GPMU_SUPER_SURF_IF_H__
-#define __GPMU_SUPER_SURF_IF_H__
+#ifndef NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H
+#define NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H

 struct nv_pmu_super_surface_hdr {
    u32 memberMask;
@@ -75,4 +75,4 @@ struct nv_pmu_super_surface {
 	} therm;
 };

-#endif /* __GPMU_SUPER_SURF_IF_H__ */
+#endif /* NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H */
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFACR_H_
-#define _GPMUIFACR_H_
+#ifndef NVGPU_PMUIF_GPMUIF_ACR_H
+#define NVGPU_PMUIF_GPMUIF_ACR_H

 /* ACR Commands/Message structures */

@@ -156,4 +156,4 @@ struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons {
 	u32  scratch[1];
 };

-#endif /* _GPMUIFACR_H_ */
+#endif /* NVGPU_PMUIF_GPMUIF_ACR_H */
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFAP_H_
-#define _GPMUIFAP_H_
+#ifndef NVGPU_PMUIF_GPMUIF_AP_H
+#define NVGPU_PMUIF_GPMUIF_AP_H

 /* PMU Command/Message Interfaces for Adaptive Power */
 /* Macro to get Histogram index */
@@ -253,4 +253,4 @@ struct pmu_ap {
 	struct ap_ctrl		ap_ctrl[PMU_AP_CTRL_ID_MAX];
 };

-#endif /* _GPMUIFAP_H_*/
+#endif /* NVGPU_PMUIF_GPMUIF_AP_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFCMN_H_
-#define _GPMUIFCMN_H_
+#ifndef NVGPU_PMUIF_GPMUIF_CMN_H
+#define NVGPU_PMUIF_GPMUIF_CMN_H

 /*
 * Defines the logical queue IDs that must be used when submitting
@@ -139,4 +139,4 @@ struct nv_pmu_rpc_header {
 	u32  exec_time_pmu_ns;
 };

-#endif /* _GPMUIFCMN_H_*/
+#endif /* NVGPU_PMUIF_GPMUIF_CMN_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFPERFMON_H_
-#define _GPMUIFPERFMON_H_
+#ifndef NVGPU_PMUIF_GPMUIF_PERFMON_H
+#define NVGPU_PMUIF_GPMUIF_PERFMON_H

 /*perfmon task defines*/

@@ -238,4 +238,4 @@ struct nv_pmu_rpc_struct_perfmon_query {
 	u32 scratch[1];
 };

-#endif /* _GPMUIFPERFMON_H_ */
+#endif /* NVGPU_PMUIF_GPMUIF_PERFMON_H */
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFPG_H_
-#define _GPMUIFPG_H_
+#ifndef NVGPU_PMUIF_GPMUIF_PG_H
+#define NVGPU_PMUIF_GPMUIF_PG_H

 #include "gpmuif_ap.h"
 #include "gpmuif_pg_rppg.h"
@@ -409,4 +409,4 @@ struct pmu_pg_stats {
 	u32 pg_gating_deny_cnt;
 };

-#endif /* _GPMUIFPG_H_*/
+#endif /* NVGPU_PMUIF_GPMUIF_PG_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFRPPG_H_
-#define _GPMUIFRPPG_H_
+#ifndef NVGPU_PMUIF_GPMUIF_PG_RPPG_H
+#define NVGPU_PMUIF_GPMUIF_PG_RPPG_H

 #define NV_PMU_RPPG_CTRL_ID_GR    (0x0000)
 #define NV_PMU_RPPG_CTRL_ID_MS    (0x0001)
@@ -107,4 +107,4 @@ enum {
 	NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0,
 };

-#endif
+#endif /* NVGPU_PMUIF_GPMUIF_PG_RPPG_H */
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFPMU_H_
-#define _GPMUIFPMU_H_
+#ifndef NVGPU_PMUIF_GPMUIF_PMU_H
+#define NVGPU_PMUIF_GPMUIF_PMU_H

 #include <nvgpu/flcnif_cmn.h>
 #include "gpmuif_cmn.h"
@@ -190,4 +190,4 @@ struct pmu_rc_msg {
 	struct pmu_rc_msg_unhandled_cmd unhandled_cmd;
 };

-#endif /* _GPMUIFPMU_H_*/
+#endif /* NVGPU_PMUIF_GPMUIF_PMU_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFBIOS_H_
-#define _GPMUIFBIOS_H_
+#ifndef NVGPU_PMUIF_GPMUIFBIOS_H
+#define NVGPU_PMUIF_GPMUIFBIOS_H

 struct nv_pmu_bios_vfield_register_segment_super {
 	u8 type;
@@ -47,4 +47,4 @@ union nv_pmu_bios_vfield_register_segment {
 };


-#endif /* _GPMUIFBIOS_H_*/
+#endif /* NVGPU_PMUIF_GPMUIFBIOS_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFBOARDOBJ_H_
-#define _GPMUIFBOARDOBJ_H_
+#ifndef NVGPU_PMUIF_GPMUIFBOARDOBJ_H
+#define NVGPU_PMUIF_GPMUIFBOARDOBJ_H

 #include <nvgpu/flcnif_cmn.h>
 #include "ctrl/ctrlboardobj.h"
@@ -231,4 +231,4 @@ struct nv_pmu_rpc_struct_board_obj_grp_cmd
    u32  scratch[1];
 };

-#endif /*  _GPMUIFBOARDOBJ_H_ */
+#endif /*  NVGPU_PMUIF_GPMUIFBOARDOBJ_H */
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
@@ -20,8 +20,8 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#ifndef _GPMUIFCLK_H_
-#define _GPMUIFCLK_H_
+#ifndef NVGPU_PMUIF_GPMUIFCLK_H
+#define NVGPU_PMUIF_GPMUIFCLK_H

 #include "ctrl/ctrlboardobj.h"
 #include "ctrl/ctrlvolt.h"
@@ -555,4 +555,4 @@ union nv_pmu_clk_clk_fll_device_boardobj_get_status_union {

 NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device);

-#endif /*_GPMUIFCLK_H_*/
+#endif /*NVGPU_PMUIF_GPMUIFCLK_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFPERF_H_
-#define _GPMUIFPERF_H_
+#ifndef NVGPU_PMUIF_GPMUIFPERF_H
+#define NVGPU_PMUIF_GPMUIFPERF_H

 #include "gpmuifvolt.h"
 #include "gpmuifperfvfe.h"
@@ -151,4 +151,4 @@ struct nv_pmu_perf_msg {
 	};
 };

-#endif  /* _GPMUIFPERF_H_*/
+#endif  /* NVGPU_PMUIF_GPMUIFPERF_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFPERFVFE_H_
-#define _GPMUIFPERFVFE_H_
+#ifndef NVGPU_PMUIF_GPMUIFPERFVFE_H
+#define NVGPU_PMUIF_GPMUIFPERFVFE_H

 #include "gpmuifbios.h"
 #include "gpmuifboardobj.h"
@@ -203,4 +203,4 @@ union nv_pmu_perf_vfe_equ_boardobj_set_union {

 NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ);

-#endif  /* _GPMUIFPERFVFE_H_*/
+#endif  /* NVGPU_PMUIF_GPMUIFPERFVFE_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -20,8 +20,8 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#ifndef _GPMUIFPMGR_H_
-#define _GPMUIFPMGR_H_
+#ifndef NVGPU_PMUIF_GPMUIFPMGR_H
+#define NVGPU_PMUIF_GPMUIFPMGR_H

 #include "ctrl/ctrlpmgr.h"
 #include "gpmuifboardobj.h"
@@ -440,4 +440,4 @@ struct nv_pmu_pmgr_msg {
 	};
 };

-#endif
+#endif /* NVGPU_PMUIF_GPMUIFPMGR_H */
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFSEQ_H_
-#define _GPMUIFSEQ_H_
+#ifndef NVGPU_PMUIF_GPMUIFSEQ_H
+#define NVGPU_PMUIF_GPMUIFSEQ_H

 #include <nvgpu/flcnif_cmn.h>

@@ -79,4 +79,4 @@ struct nv_pmu_seq_msg {
 	};
 };

-#endif
+#endif /* NVGPU_PMUIF_GPMUIFSEQ_H */
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -20,8 +20,8 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#ifndef _GPMUIFTHERM_H_
-#define _GPMUIFTHERM_H_
+#ifndef NVGPU_PMUIF_GPMUIFTHERM_H
+#define NVGPU_PMUIF_GPMUIFTHERM_H

 #include <nvgpu/flcnif_cmn.h>

@@ -98,5 +98,5 @@ struct nv_pmu_therm_msg {
 	};
 };

-#endif
+#endif /* NVGPU_PMUIF_GPMUIFTHERM_H */

--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -20,8 +20,8 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#ifndef _GPMUIFTHERMSENSOR_H_
-#define _GPMUIFTHERMSENSOR_H_
+#ifndef NVGPU_PMUIF_GPMUIFTHERMSENSOR_H
+#define NVGPU_PMUIF_GPMUIFTHERMSENSOR_H

 #include "ctrl/ctrltherm.h"
 #include "gpmuifboardobj.h"
@@ -102,4 +102,4 @@ union nv_pmu_therm_therm_channel_boardobj_set_union {

 NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel);

-#endif
+#endif /* NVGPU_PMUIF_GPMUIFTHERMSENSOR_H */
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _GPMUIFVOLT_H_
-#define _GPMUIFVOLT_H_
+#ifndef NVGPU_PMUIF_GPMUIFVOLT_H
+#define NVGPU_PMUIF_GPMUIFVOLT_H

 #include "gpmuifboardobj.h"
 #include <nvgpu/flcnif_cmn.h>
@@ -399,4 +399,4 @@ struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage {
 	u32  scratch[1];
 };

-#endif  /* _GPMUIFVOLT_H_*/
+#endif  /* NVGPU_PMUIF_GPMUIFVOLT_H*/
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -19,8 +19,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef _NVGPUGPMUCMDIF_H_
-#define _NVGPUGPMUCMDIF_H_
+#ifndef NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H
+#define NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H

 #include <nvgpu/flcnif_cmn.h>
 #include "gpmuif_cmn.h"
@@ -140,4 +140,4 @@ struct pmu_msg {
 #define PMU_UNIT_ID_IS_VALID(id)		\
 		(((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START))

-#endif /* _NVGPUGPMUCMDIF_H_*/
+#endif /* NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H*/