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gpu: nvgpu: vgpu: Add CE engine to engine list

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Add CE engine to vgpu engine list. CE engine is defined differently
for different GPUs, so we also add HAL for initializing the engine
info.

Bug 1780185

Change-Id: I5ae265551feac08d0c4d45402dd3277514e62b2d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1169720
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Tested-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
This commit is contained in:
Terje Bergstrom
2016-06-22 14:44:22 -07:00
parent 41ec68376f
commit 475af509e1
5 changed files with 23 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -279,7 +279,7 @@ int gk20a_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
return ret; return ret;
} }
static int init_engine_info(struct fifo_gk20a *f) int gk20a_fifo_init_engine_info(struct fifo_gk20a *f)
{ {
struct gk20a *g = f->g; struct gk20a *g = f->g;
struct device *d = dev_from_gk20a(g); struct device *d = dev_from_gk20a(g);
@@ -796,7 +796,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g)
for (i = 0; i < f->num_pbdma; ++i) for (i = 0; i < f->num_pbdma; ++i)
f->pbdma_map[i] = gk20a_readl(g, fifo_pbdma_map_r(i)); f->pbdma_map[i] = gk20a_readl(g, fifo_pbdma_map_r(i));
init_engine_info(f); g->ops.fifo.init_engine_info(f);
init_runlist(g, f); init_runlist(g, f);
@@ -3082,4 +3082,5 @@ void gk20a_init_fifo(struct gpu_ops *gops)
/* gk20a doesn't support device_info_data packet parsing */ /* gk20a doesn't support device_info_data packet parsing */
gops->fifo.device_info_data_parse = NULL; gops->fifo.device_info_data_parse = NULL;
gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
gops->fifo.init_engine_info = gk20a_fifo_init_engine_info;
} }

3
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
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@@ -250,4 +250,7 @@ bool gk20a_fifo_is_valid_runlist_id(struct gk20a *g, u32 runlist_id);
int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 hw_chid, int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 hw_chid,
bool add, bool wait_for_finish); bool add, bool wait_for_finish);
int gk20a_fifo_init_engine_info(struct fifo_gk20a *f);
#endif /*__GR_GK20A_H__*/ #endif /*__GR_GK20A_H__*/

1
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -352,6 +352,7 @@ struct gpu_ops {
struct channel_gk20a *ch); struct channel_gk20a *ch);
int (*tsg_unbind_channel)(struct channel_gk20a *ch); int (*tsg_unbind_channel)(struct channel_gk20a *ch);
u32 (*eng_runlist_base_size)(void); u32 (*eng_runlist_base_size)(void);
int (*init_engine_info)(struct fifo_gk20a *f);
} fifo; } fifo;
struct pmu_v { struct pmu_v {
/*used for change of enum zbc update cmd id from ver 0 to ver1*/ /*used for change of enum zbc update cmd id from ver 0 to ver1*/

1
drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
View File

@@ -155,4 +155,5 @@ void gm20b_init_fifo(struct gpu_ops *gops)
gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type; gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
gops->fifo.device_info_data_parse = gm20b_device_info_data_parse; gops->fifo.device_info_data_parse = gm20b_device_info_data_parse;
gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
gops->fifo.init_engine_info = gk20a_fifo_init_engine_info;
} }

22
drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
View File

@@ -160,22 +160,29 @@ static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
return (err || msg.ret) ? -ENOMEM : 0; return (err || msg.ret) ? -ENOMEM : 0;
} }
static int init_engine_info(struct fifo_gk20a *f) static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f)
{ {
struct fifo_engine_info_gk20a *gr_info; struct fifo_engine_info_gk20a *gr_info;
struct fifo_engine_info_gk20a *ce_info;
const u32 gr_sw_id = ENGINE_GR_GK20A; const u32 gr_sw_id = ENGINE_GR_GK20A;
const u32 ce_sw_id = ENGINE_GRCE_GK20A;
gk20a_dbg_fn(""); gk20a_dbg_fn("");
/* all we really care about finding is the graphics entry */ f->num_engines = 2;
/* especially early on in sim it probably thinks it has more */
f->num_engines = 1;
gr_info = f->engine_info + gr_sw_id; gr_info = &f->engine_info[0];
/* FIXME: retrieve this from server */ /* FIXME: retrieve this from server */
gr_info->runlist_id = 0; gr_info->runlist_id = 0;
f->active_engines_list[0] = gr_sw_id; gr_info->engine_enum = gr_sw_id;
f->active_engines_list[0] = 0;
ce_info = &f->engine_info[1];
ce_info->runlist_id = 0;
ce_info->inst_id = 2;
ce_info->engine_enum = ce_sw_id;
f->active_engines_list[1] = 1;
return 0; return 0;
} }
@@ -292,7 +299,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g)
} }
memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32))); memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32)));
init_engine_info(f); g->ops.fifo.init_engine_info(f);
init_runlist(g, f); init_runlist(g, f);
@@ -778,4 +785,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops)
gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave;
gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice;
gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch; gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch;
gops->fifo.init_engine_info = vgpu_fifo_init_engine_info;
} }