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gpu: nvgpu: pstate interface update
lpwr_entry_idx member is required to map pstate with lwpr tables JIRA DNVGPU-71 Change-Id: I4cad54c61dec7ad7e3c1a60178938d0eeaf65e24 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247303 (cherry-picked from commit b1f6e0036922d2104b3d08548219e72a38f2e231) Reviewed-on: http://git-master/r/1267403 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Deepak Nibade
parent
fd2b0a4860
commit
476f44a0a4
@@ -177,6 +177,7 @@ int pstate_construct_super(struct gk20a *g, struct boardobj **ppboardobj,
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pstate->num = ptmppstate->num;
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pstate->clklist = ptmppstate->clklist;
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pstate->lpwr_entry_idx = ptmppstate->lpwr_entry_idx;
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return 0;
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}
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@@ -236,6 +237,7 @@ static int parse_pstate_entry_5x(struct gk20a *g,
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pstate->super.type = CTRL_PERF_PSTATE_TYPE_3X;
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pstate->num = 0x0F - entry->pstate_level;
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pstate->clklist.num_info = hdr->clock_entry_count;
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pstate->lpwr_entry_idx = entry->lpwr_entry_idx;
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gk20a_dbg_info("pstate P%u", pstate->num);
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@@ -41,6 +41,7 @@ struct clk_set_info_list {
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struct pstate {
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struct boardobj super;
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u32 num;
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u8 lpwr_entry_idx;
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struct clk_set_info_list clklist;
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};
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