gpu: nvgpu: hide priv cmdbuf gva and size

Add an accessor function in the priv cmdbuf object for gva and size to
be written in a gpfifo entry once the cmdbuf build is finished. This
helps in eventually hiding the struct priv_cmd_entry as an
implementation detail.

Add a sanity check to verify that the buffer has been filled exactly to
the requested size. The cmdbufs are used to hold wait and increment
commands for syncpoints or gpu semaphores. A prefence buffer can hold a
number of wait commands of equal size, and the postfence buffer holds
exactly one increment.

Jira NVGPU-4548

Change-Id: I83132bf6de52794ecc419e033e9f4599e488fd68
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325102
(cherry picked from commit d1831463a487666017c4c80fab0292a0b85c7d83)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331339
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c

@@ -30,6 +30,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/priv_cmdbuf.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/trace.h>
 
 struct priv_cmd_queue {
 	struct nvgpu_mem mem;
@@ -256,3 +257,24 @@ void nvgpu_priv_cmdbuf_append_zeros(struct gk20a *g, struct priv_cmd_entry *e,
 			0, entries * sizeof(u32));
 	e->fill_off += entries;
 }
+
+void nvgpu_priv_cmdbuf_finish(struct gk20a *g, struct priv_cmd_entry *e,
+		u64 *gva, u32 *size)
+{
+	/*
+	 * The size is written to the pushbuf entry, so make sure this buffer
+	 * is complete at this point. The responsibility of the channel sync is
+	 * to be consistent in allocation and usage, and the matching size and
+	 * add gops (e.g., get_wait_cmd_size, add_wait_cmd) help there.
+	 */
+	nvgpu_assert(e->fill_off == e->size);
+
+#ifdef CONFIG_NVGPU_TRACE
+	if (e->mem->aperture == APERTURE_SYSMEM) {
+		trace_gk20a_push_cmdbuf(g->name, 0, e->size, 0,
+				(u32 *)e->mem->cpu_va + e->off);
+	}
+#endif
+	*gva = e->gva;
+	*size = e->size;
+}

drivers/gpu/nvgpu/common/fifo/submit.c

@@ -199,21 +199,16 @@ static void nvgpu_submit_append_priv_cmdbuf(struct nvgpu_channel *c,
 	struct gk20a *g = c->g;
 	struct nvgpu_mem *gpfifo_mem = &c->gpfifo.mem;
 	struct nvgpu_gpfifo_entry gpfifo_entry;
+	u64 gva;
+	u32 size;
 
-	g->ops.pbdma.format_gpfifo_entry(g, &gpfifo_entry,
+	nvgpu_priv_cmdbuf_finish(g, cmd, &gva, &size);
-			cmd->gva, cmd->size);
+	g->ops.pbdma.format_gpfifo_entry(g, &gpfifo_entry, gva, size);
 
 	nvgpu_mem_wr_n(g, gpfifo_mem,
 			c->gpfifo.put * (u32)sizeof(gpfifo_entry),
 			&gpfifo_entry, (u32)sizeof(gpfifo_entry));
 
-#ifdef CONFIG_NVGPU_TRACE
-	if (cmd->mem->aperture == APERTURE_SYSMEM) {
-		trace_gk20a_push_cmdbuf(g->name, 0, cmd->size, 0,
-				(u32 *)cmd->mem->cpu_va + cmd->off);
-	}
-#endif
-
 	c->gpfifo.put = (c->gpfifo.put + 1U) & (c->gpfifo.entry_num - 1U);
 }
 

drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h

@@ -54,4 +54,7 @@ void nvgpu_priv_cmdbuf_append(struct gk20a *g, struct priv_cmd_entry *e,
 void nvgpu_priv_cmdbuf_append_zeros(struct gk20a *g, struct priv_cmd_entry *e,
 		u32 entries);
 
+void nvgpu_priv_cmdbuf_finish(struct gk20a *g, struct priv_cmd_entry *e,
+		u64 *gva, u32 *size);
+
 #endif