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git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
gpu: nvgpu: Prune redundant cache maintenance
Remove redundant cache maintenance operations. Instance blocks and graphics context buffers are uncached, so they do not need any cache maintenance. Bug 1421824 Change-Id: Ie0be67bf0be493d9ec9e6f8226f2f9359cba9f54 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406948
This commit is contained in:
Terje Bergstrom
committed by
Dan Willemsen
Dan Willemsen
parent
3e5c123862
commit
48239f5f8c
@@ -128,8 +128,6 @@ int channel_gk20a_commit_va(struct channel_gk20a *c)
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gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_hi_w(),
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ram_in_adr_limit_hi_f(u64_hi32(c->vm->va_limit)));
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gk20a_mm_l2_invalidate(c->g);
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return 0;
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}
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@@ -159,8 +157,6 @@ static int channel_gk20a_commit_userd(struct channel_gk20a *c)
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pbdma_userd_target_vid_mem_f() |
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pbdma_userd_hi_addr_f(addr_hi));
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gk20a_mm_l2_invalidate(c->g);
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return 0;
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}
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@@ -183,9 +179,6 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c,
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/* preempt the channel */
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WARN_ON(gk20a_fifo_preempt_channel(c->g, c->hw_chid));
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/* flush GPU cache */
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gk20a_mm_l2_flush(c->g, true);
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/* value field is 8 bits long */
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while (value >= 1 << 8) {
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value >>= 1;
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@@ -209,8 +202,6 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c,
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gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) |
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ccsr_channel_enable_set_true_f());
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gk20a_mm_l2_invalidate(c->g);
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return 0;
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}
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@@ -277,8 +268,6 @@ static int channel_gk20a_setup_ramfc(struct channel_gk20a *c,
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gk20a_mem_wr32(inst_ptr, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
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gk20a_mm_l2_invalidate(c->g);
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return 0;
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}
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@@ -299,8 +288,6 @@ static int channel_gk20a_setup_userd(struct channel_gk20a *c)
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gk20a_mem_wr32(c->userd_cpu_va, ram_userd_gp_get_w(), 0);
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gk20a_mem_wr32(c->userd_cpu_va, ram_userd_gp_put_w(), 0);
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gk20a_mm_l2_invalidate(c->g);
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return 0;
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}
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@@ -649,8 +636,6 @@ void gk20a_free_channel(struct channel_gk20a *ch, bool finish)
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ch->gpfifo.cpu_va = NULL;
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ch->gpfifo.iova = 0;
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gk20a_mm_l2_invalidate(ch->g);
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memset(&ch->gpfifo, 0, sizeof(struct gpfifo_desc));
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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@@ -1155,8 +1140,6 @@ static int gk20a_alloc_channel_gpfifo(struct channel_gk20a *c,
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channel_gk20a_setup_userd(c);
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channel_gk20a_commit_userd(c);
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gk20a_mm_l2_invalidate(c->g);
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/* TBD: setup engine contexts */
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err = channel_gk20a_alloc_priv_cmdbuf(c);
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@@ -538,9 +538,7 @@ static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va)
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gk20a_dbg_fn("");
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/* flush gpu_va before commit */
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gk20a_mm_fb_flush(c->g);
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gk20a_mm_l2_flush(c->g, true);
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inst_ptr = c->inst_block.cpuva;
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if (!inst_ptr)
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@@ -556,8 +554,6 @@ static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va)
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gk20a_mem_wr32(inst_ptr, ram_in_gr_wfi_ptr_hi_w(),
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ram_in_gr_wfi_ptr_hi_f(addr_hi));
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gk20a_mm_l2_invalidate(c->g);
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return 0;
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}
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@@ -600,8 +596,6 @@ int gr_gk20a_ctx_patch_write_end(struct gk20a *g,
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vunmap(ch_ctx->patch_ctx.cpu_va);
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ch_ctx->patch_ctx.cpu_va = NULL;
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gk20a_mm_l2_invalidate(g);
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return 0;
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}
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@@ -718,10 +712,7 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c,
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}
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}
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/* Channel gr_ctx buffer is gpu cacheable.
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Flush and invalidate before cpu update. */
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gk20a_mm_fb_flush(g);
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gk20a_mm_l2_flush(g, true);
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gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_o(), 0,
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ch_ctx->zcull_ctx.ctx_sw_mode);
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@@ -736,7 +727,6 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c,
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goto clean_up;
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}
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}
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gk20a_mm_l2_invalidate(g);
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clean_up:
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vunmap(ctx_ptr);
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@@ -1466,10 +1456,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
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ctx_header_words = roundup(ctx_header_bytes, sizeof(u32));
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ctx_header_words >>= 2;
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/* Channel gr_ctx buffer is gpu cacheable.
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Flush before cpu read. */
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gk20a_mm_fb_flush(g);
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gk20a_mm_l2_flush(g, false);
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for (i = 0; i < ctx_header_words; i++) {
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data = gk20a_mem_rd32(ctx_ptr, i);
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@@ -1504,8 +1491,6 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
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gr->ctx_vars.golden_image_initialized = true;
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gk20a_mm_l2_invalidate(g);
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gk20a_writel(g, gr_fecs_current_ctx_r(),
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gr_fecs_current_ctx_valid_false_f());
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@@ -1537,7 +1522,6 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g,
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/* Channel gr_ctx buffer is gpu cacheable.
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Flush and invalidate before cpu update. */
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gk20a_mm_fb_flush(g);
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gk20a_mm_l2_flush(g, true);
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ctx_ptr = vmap(ch_ctx->gr_ctx.pages,
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PAGE_ALIGN(ch_ctx->gr_ctx.size) >> PAGE_SHIFT,
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@@ -1555,8 +1539,6 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g,
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vunmap(ctx_ptr);
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gk20a_mm_l2_invalidate(g);
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return 0;
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}
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@@ -1580,7 +1562,6 @@ static int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
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/* Channel gr_ctx buffer is gpu cacheable.
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Flush and invalidate before cpu update. */
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gk20a_mm_fb_flush(g);
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gk20a_mm_l2_flush(g, true);
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ctx_ptr = vmap(ch_ctx->gr_ctx.pages,
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PAGE_ALIGN(ch_ctx->gr_ctx.size) >> PAGE_SHIFT,
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@@ -1636,8 +1617,6 @@ static int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
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vunmap(ctx_ptr);
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gk20a_mm_l2_invalidate(g);
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if (tegra_platform_is_linsim()) {
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u32 inst_base_ptr =
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u64_lo32(c->inst_block.cpu_pa
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@@ -2716,7 +2695,6 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c,
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}
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c->first_init = true;
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}
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gk20a_mm_l2_invalidate(g);
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c->num_objects++;
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@@ -4223,8 +4201,6 @@ restore_fe_go_idle:
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sw_method_init->l[i].addr);
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}
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gk20a_mm_l2_invalidate(g);
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err = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
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if (err)
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goto out;
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@@ -5797,10 +5773,6 @@ int gr_gk20a_ctx_patch_smpc(struct gk20a *g,
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/* we're not caching these on cpu side,
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but later watch for it */
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/* the l2 invalidate in the patch_write
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* would be too early for this? */
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gk20a_mm_l2_invalidate(g);
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return 0;
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}
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}
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@@ -6538,10 +6510,7 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
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goto cleanup;
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}
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/* Channel gr_ctx buffer is gpu cacheable; so flush and invalidate.
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* There should be no on-going/in-flight references by the gpu now. */
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gk20a_mm_fb_flush(g);
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gk20a_mm_l2_flush(g, true);
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/* write to appropriate place in context image,
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* first have to figure out where that really is */
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@@ -1937,8 +1937,6 @@ static int gk20a_vm_put_empty(struct vm_gk20a *vm, u64 vaddr,
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vaddr += pgsz;
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}
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gk20a_mm_l2_flush(mm->g, true);
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return 0;
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err_unmap:
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