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gpu: nvgpu: MISRA 21.2 fixes: __nvgpu_set_enabled()

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Rename __nvgpu_set_enabled() to nvgpu_set_enabled(). The original
double underscore was present to indicate that this function is a
function with potentially unintended side effects (enabling a feature
has wide ranging impact).

To not lose this documentation a comment was added to convey that this
function must be used with care.

JIRA NVGPU-1029

Change-Id: I8bfc6fa4c17743f9f8056cb6a7a0f66229ca2583
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989434
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2019-01-07 10:26:39 -08:00
committed by mobile promotions
parent 4ce9c114d5
commit 489236d181
39 changed files with 203 additions and 199 deletions
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14
drivers/gpu/nvgpu/common/init/nvgpu_init.c
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@@ -504,11 +504,11 @@ int gk20a_wait_for_idle(struct gk20a *g)
int gk20a_init_gpu_characteristics(struct gk20a *g)
{
__nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true);
__nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true);
if ((g->ops.mm.support_sparse != NULL) && g->ops.mm.support_sparse(g)) {
__nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true);
}
/*
@@ -516,7 +516,7 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
* anything that depends on job tracking. (Here, fast means strictly no
* metadata, just the gpfifo contents are copied and gp_put updated).
*/
__nvgpu_set_enabled(g,
nvgpu_set_enabled(g,
NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING,
true);
@@ -527,16 +527,16 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
* that depends on deferred cleanup.
*/
if (!nvgpu_channel_sync_needs_os_fence_framework(g)) {
__nvgpu_set_enabled(g,
nvgpu_set_enabled(g,
NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL,
true);
}
__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG, true);
if (g->ops.clk_arb.get_arbiter_clk_domains != NULL &&
g->ops.clk.support_clk_freq_controller) {
__nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true);
}
g->ops.gr.detect_sm_arch(g);