nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: MISRA 21.2 fixes: __nvgpu_set_enabled()

Browse Source 
Rename __nvgpu_set_enabled() to nvgpu_set_enabled(). The original
double underscore was present to indicate that this function is a
function with potentially unintended side effects (enabling a feature
has wide ranging impact).

To not lose this documentation a comment was added to convey that this
function must be used with care.

JIRA NVGPU-1029

Change-Id: I8bfc6fa4c17743f9f8056cb6a7a0f66229ca2583
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989434
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2019-01-07 10:26:39 -08:00
committed by mobile promotions
parent 4ce9c114d5
commit 489236d181
39 changed files with 203 additions and 199 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
userspace/units/fuse/nvgpu-fuse-gm20b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -309,7 +309,7 @@ int test_fuse_gm20b_check_fmodel(struct unit_module *m,
int ret = UNIT_SUCCESS;
int result;
__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
result = g->ops.fuse.check_priv_security(g);
if (result != 0) {
@@ -328,6 +328,6 @@ int test_fuse_gm20b_check_fmodel(struct unit_module *m,
ret = UNIT_FAIL;
}
__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
return ret;
}

7
userspace/units/fuse/nvgpu-fuse-gp10b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -242,7 +242,7 @@ int test_fuse_gp10b_check_fmodel(struct unit_module *m,
int ret = UNIT_SUCCESS;
int result;
__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
result = g->ops.fuse.check_priv_security(g);
if (result != 0) {
@@ -261,7 +261,6 @@ int test_fuse_gp10b_check_fmodel(struct unit_module *m,
ret = UNIT_FAIL;
}
__nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
return ret;
}

8
userspace/units/mm/gmmu/page_table/page_table.c
View File

@@ -266,12 +266,12 @@ static const struct nvgpu_sgt_ops nvgpu_sgt_posix_ops = {
static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU)
{
if (is_iGPU) {
__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
/* Features below are mostly to cover corner cases */
__nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
} else {
__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
}
}

4
userspace/units/mm/gmmu/pd_cache/pd_cache.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -726,7 +726,7 @@ cleanup:
static int test_pd_cache_env_init(struct unit_module *m,
struct gk20a *g, void *args)
{
__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
return UNIT_SUCCESS;
}

4
userspace/units/posix/fault-injection/posix-fault-injection.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -29,7 +29,7 @@
static int test_fault_injection_init(struct unit_module *m,
struct gk20a *g, void *__args)
{
__nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
return UNIT_SUCCESS;
}

6
userspace/units/pramin/nvgpu-pramin.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -483,7 +483,7 @@ static int test_pramin_nvgpu_dying(struct unit_module *m, struct gk20a *g,
if (init_test_env(m, g) != 0) {
unit_return_fail(m, "Module init failed\n");
}
__nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
/*
* When the GPU is dying, PRAMIN should prevent any accesses, so
* pointers to nvgpu_mem and destination data don't matter and can be
@@ -493,7 +493,7 @@ static int test_pramin_nvgpu_dying(struct unit_module *m, struct gk20a *g,
nvgpu_pramin_rd_n(g, NULL, 0, 1, NULL);
/* Restore GPU driver state for other tests */
__nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, false);
nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, false);
return UNIT_SUCCESS;
}