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gpu: nvgpu: gv11b: set only valid soc credits

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Only for following instances,  mssnvlink <-> hshub will
be interacting in gv11b:

NV_ADDRESS_MAP_MSS_NVLINK_1_BASE
NV_ADDRESS_MAP_MSS_NVLINK_2_BASE 
NV_ADDRESS_MAP_MSS_NVLINK_3_BASE
NV_ADDRESS_MAP_MSS_NVLINK_4_BASE
 
NV_ADDRESS_MAP_MSS_NVLINK_0_BASE doesnt interact with gv11b hshub,
so don't set those credits.

GPUT19X-116

Change-Id: I8c6737293699444ddb1e27936f1c4a2e61871c29
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1493641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2017-05-31 21:56:20 -07:00
committed by mobile promotions
parent 3972739823
commit 48afa1c69c
1 changed files with 0 additions and 6 deletions
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6
drivers/gpu/nvgpu/gv11b/fb_gv11b.c
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@@ -31,7 +31,6 @@
static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
{
void __iomem *soc0 = ioremap(0x01f00010, 4096); //MSS_NVLINK_0_BASE
void __iomem *soc1 = ioremap(0x01f20010, 4096); //MSS_NVLINK_1_BASE
void __iomem *soc2 = ioremap(0x01f40010, 4096); //MSS_NVLINK_2_BASE
void __iomem *soc3 = ioremap(0x01f60010, 4096); //MSS_NVLINK_3_BASE
@@ -41,11 +40,6 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
/* TODO : replace this code with proper nvlink API */
nvgpu_info(g, "init nvlink soc credits");
val = readl_relaxed(soc0);
writel_relaxed(val, soc0);
val = readl_relaxed(soc0 + 4);
writel_relaxed(val, soc0 + 4);
val = readl_relaxed(soc1);
writel_relaxed(val, soc1);
val = readl_relaxed(soc1 + 4);