gpu: nvgpu: move fecs related structures to gr_falcon_priv.h

Moved following structure defs from gr_gk20a.h to gr_falcon_priv.h:
gk20a_ctxsw_bootloader_desc -> nvgpu_ctxsw_bootloader_desc
fecs_method_op_gk20a -> nvgpu_fecs_method_op

Updated code to use these new structure defs.

JIRA NVGPU-1881

Change-Id: Ie0f06ce6f2bfeb1b4ec4b01643c206bd863a7a88
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089317
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -33,6 +33,8 @@
 #include <nvgpu/acr.h>
 #include <nvgpu/power_features/pg.h>
 
+#include "gr_falcon_priv.h"
+
 int nvgpu_gr_falcon_bind_fecs_elpg(struct gk20a *g)
 {
 	struct nvgpu_pmu *pmu = &g->pmu;
@@ -187,7 +189,7 @@ static void nvgpu_gr_falcon_init_ctxsw_ucode_segment(
 
 static void nvgpu_gr_falcon_init_ctxsw_ucode_segments(
 	struct gk20a_ctxsw_ucode_segments *segments, u32 *offset,
-	struct gk20a_ctxsw_bootloader_desc *bootdesc,
+	struct nvgpu_ctxsw_bootloader_desc *bootdesc,
 	u32 code_size, u32 data_size)
 {
 	u32 boot_size = ALIGN(bootdesc->size, sizeof(u32));
@@ -231,8 +233,8 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g)
 {
 	struct mm_gk20a *mm = &g->mm;
 	struct vm_gk20a *vm = mm->pmu.vm;
-	struct gk20a_ctxsw_bootloader_desc *fecs_boot_desc;
-	struct gk20a_ctxsw_bootloader_desc *gpccs_boot_desc;
+	struct nvgpu_ctxsw_bootloader_desc *fecs_boot_desc;
+	struct nvgpu_ctxsw_bootloader_desc *gpccs_boot_desc;
 	struct nvgpu_firmware *fecs_fw;
 	struct nvgpu_firmware *gpccs_fw;
 	u32 *fecs_boot_image;
@@ -249,7 +251,7 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g)
 
 	fecs_boot_desc = (void *)fecs_fw->data;
 	fecs_boot_image = (void *)(fecs_fw->data +
-				sizeof(struct gk20a_ctxsw_bootloader_desc));
+				sizeof(struct nvgpu_ctxsw_bootloader_desc));
 
 	gpccs_fw = nvgpu_request_firmware(g, GK20A_GPCCS_UCODE_IMAGE, 0);
 	if (gpccs_fw == NULL) {
@@ -260,7 +262,7 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g)
 
 	gpccs_boot_desc = (void *)gpccs_fw->data;
 	gpccs_boot_image = (void *)(gpccs_fw->data +
-				sizeof(struct gk20a_ctxsw_bootloader_desc));
+				sizeof(struct nvgpu_ctxsw_bootloader_desc));
 
 	ucode_size = 0;
 	nvgpu_gr_falcon_init_ctxsw_ucode_segments(&ucode_info->fecs,

drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GR_FALCON_PRIV_H
+#define GR_FALOCN_PRIV_H
+
+#include <nvgpu/types.h>
+
+struct nvgpu_fecs_method_op {
+	struct {
+		u32 addr;
+		u32 data;
+	} method;
+
+	struct {
+		u32 id;
+		u32 data;
+		u32 clr;
+		u32 *ret;
+		u32 ok;
+		u32 fail;
+	} mailbox;
+
+	struct {
+		u32 ok;
+		u32 fail;
+	} cond;
+
+};
+
+struct nvgpu_ctxsw_bootloader_desc {
+	u32 start_offset;
+	u32 size;
+	u32 imem_offset;
+	u32 entry_point;
+};
+
+#endif /* GR_FALOCN_PRIV_H */
+

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -240,35 +240,6 @@ struct gk20a_ctxsw_ucode_info {
 	struct gk20a_ctxsw_ucode_segments gpccs;
 };
 
-struct gk20a_ctxsw_bootloader_desc {
-	u32 start_offset;
-	u32 size;
-	u32 imem_offset;
-	u32 entry_point;
-};
-
-struct fecs_method_op_gk20a {
-	struct {
-		u32 addr;
-		u32 data;
-	} method;
-
-	struct {
-		u32 id;
-		u32 data;
-		u32 clr;
-		u32 *ret;
-		u32 ok;
-		u32 fail;
-	} mailbox;
-
-	struct {
-		u32 ok;
-		u32 fail;
-	} cond;
-
-};
-
 struct nvgpu_warpstate {
 	u64 valid_warps[2];
 	u64 trapped_warps[2];

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c

@@ -27,6 +27,7 @@
 #include <nvgpu/power_features/pg.h>
 
 #include "gr_falcon_gm20b.h"
+#include "common/gr/gr_falcon_priv.h"
 
 #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
@@ -704,7 +705,7 @@ void gm20b_gr_falcon_set_current_ctx_invalid(struct gk20a *g)
  * We should replace most, if not all, fecs method calls to this instead.
  */
 int gm20b_gr_falcon_submit_fecs_method_op(struct gk20a *g,
-				   struct fecs_method_op_gk20a op,
+				   struct nvgpu_fecs_method_op op,
 				   bool sleepduringwait)
 {
 	struct gr_gk20a *gr = &g->gr;
@@ -747,7 +748,7 @@ int gm20b_gr_falcon_submit_fecs_method_op(struct gk20a *g,
 
 /* Sideband mailbox writes are done a bit differently */
 int gm20b_gr_falcon_submit_fecs_sideband_method_op(struct gk20a *g,
-		struct fecs_method_op_gk20a op)
+		struct nvgpu_fecs_method_op op)
 {
 	struct gr_gk20a *gr = &g->gr;
 	int ret;
@@ -778,7 +779,7 @@ int gm20b_gr_falcon_submit_fecs_sideband_method_op(struct gk20a *g,
 int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
 			u32 data, u32 *ret_val)
 {
-	struct fecs_method_op_gk20a op = {
+	struct nvgpu_fecs_method_op op = {
 		.mailbox = { .id = 0U, .data = 0U, .ret = NULL,
 			     .clr = ~U32(0U), .ok = 0U, .fail = 0U},
 		.method.data = 0U,

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h

@@ -26,7 +26,7 @@
 #include <nvgpu/types.h>
 
 struct gk20a;
-struct fecs_method_op_gk20a;
+struct nvgpu_fecs_method_op;
 
 u32 gm20b_gr_falcon_fecs_base_addr(void);
 u32 gm20b_gr_falcon_gpccs_base_addr(void);
@@ -57,9 +57,9 @@ void gm20b_gr_falcon_load_ctxsw_ucode_boot(struct gk20a *g,
 int gm20b_gr_falcon_wait_mem_scrubbing(struct gk20a *g);
 int gm20b_gr_falcon_wait_ctxsw_ready(struct gk20a *g);
 int gm20b_gr_falcon_submit_fecs_method_op(struct gk20a *g,
-	struct fecs_method_op_gk20a op, bool sleepduringwait);
+	struct nvgpu_fecs_method_op op, bool sleepduringwait);
 int gm20b_gr_falcon_submit_fecs_sideband_method_op(struct gk20a *g,
-				struct fecs_method_op_gk20a op);
+				struct nvgpu_fecs_method_op op);
 int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
 						u32 data, u32 *ret_val);
 

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b.c

@@ -25,6 +25,7 @@
 
 #include "gr_falcon_gp10b.h"
 #include "gr_falcon_gm20b.h"
+#include "common/gr/gr_falcon_priv.h"
 
 #include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 
@@ -60,7 +61,7 @@ int gp10b_gr_falcon_init_ctx_state(struct gk20a *g)
 int gp10b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
 						u32 data, u32 *ret_val)
 {
-	struct fecs_method_op_gk20a op = {
+	struct nvgpu_fecs_method_op op = {
 		.mailbox = { .id = 0U, .data = 0U, .ret = NULL,
 			     .clr = ~U32(0U), .ok = 0U, .fail = 0U},
 		.method.data = 0U,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -75,6 +75,7 @@ struct nvgpu_channel_hw_state;
 struct nvgpu_engine_status_info;
 struct nvgpu_pbdma_status_info;
 struct nvgpu_gr_config;
+struct nvgpu_fecs_method_op;
 enum nvgpu_nvlink_minion_dlcmd;
 struct nvgpu_cbc;
 struct nvgpu_mem;
@@ -577,10 +578,10 @@ struct gpu_ops {
 			int (*wait_mem_scrubbing)(struct gk20a *g);
 			int (*wait_ctxsw_ready)(struct gk20a *g);
 			int (*submit_fecs_method_op)(struct gk20a *g,
-				struct fecs_method_op_gk20a op,
+				struct nvgpu_fecs_method_op op,
 				bool sleepduringwait);
 			int (*submit_fecs_sideband_method_op)(struct gk20a *g,
-				struct fecs_method_op_gk20a op);
+				struct nvgpu_fecs_method_op op);
 			int (*ctrl_ctxsw)(struct gk20a *g, u32 fecs_method,
 				u32 fecs_data, u32 *ret_val);
 			int (*halt_pipe)(struct gk20a *g);