gpu: nvgpu: Add bundle skip sequence in MIG mode

In MIG mode, 2D, 3D, I2M and ZBC classes are not supported
by GR engine. So skip those bundle programming sequence in MIG mode.

JIRA NVGPU-5648

Change-Id: I7ac28a40367e19a3e31e63f3e25991c0ed4d2d8b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2397912
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -845,15 +845,18 @@ int nvgpu_init_gpu_characteristics(struct gk20a *g)
 	}
 #endif
 
-	/*
-	 * In MIG mode, 2D, 3D, I2M and ZBC classes are not supported by
-	 * GR engine. Default values for legacy mode (non MIG).
-	 */
-	nvgpu_set_enabled(g, NVGPU_SUPPORT_2D, true);
-	nvgpu_set_enabled(g, NVGPU_SUPPORT_3D, true);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPUTE, true);
-	nvgpu_set_enabled(g, NVGPU_SUPPORT_I2M, true);
-	nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC, true);
+
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		/*
+		 * In MIG mode, 2D, 3D, I2M and ZBC classes are not supported
+		 * by GR engine. Default values for legacy mode (non MIG).
+		 */
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_2D, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_3D, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_I2M, true);
+		nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC, true);
+	}
 
 	return 0;
 }

drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h

@@ -29,6 +29,9 @@
 #define GR_GO_IDLE_BUNDLE	0x0000e100U /* --V-B */
 #endif
 
+#define GR_PIPE_MODE_BUNDLE		0x1000U
+#define GR_PIPE_MODE_MAJOR_COMPUTE	0x00000008U
+
 struct gk20a;
 struct nvgpu_gr_ctx;
 struct nvgpu_gr_config;
@@ -67,6 +70,9 @@ void gm20b_gr_init_commit_global_attrib_cb(struct gk20a *g,
 u32 gm20b_gr_init_get_patch_slots(struct gk20a *g,
 	struct nvgpu_gr_config *config);
 
+bool gm20b_gr_init_is_allowed_sw_bundle(struct gk20a *g,
+	u32 bundle_addr, u32 bundle_value, int *context);
+
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void gm20b_gr_init_gpc_mmu(struct gk20a *g);
 #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP

drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c

@@ -441,6 +441,43 @@ u32 gm20b_gr_init_get_patch_slots(struct gk20a *g,
 	return PATCH_CTX_SLOTS_PER_PAGE;
 }
 
+bool gm20b_gr_init_is_allowed_sw_bundle(struct gk20a *g,
+	u32 bundle_addr, u32 bundle_value, int *context)
+{
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Allowed bundle addr[%x] value[%x] ",
+			bundle_addr, bundle_value);
+		return true;
+	}
+	/*
+	 * Capture whether the current bundle is compute or not.
+	 * Store in context.
+	 */
+	if (gr_pipe_bundle_address_value_v(bundle_addr) ==
+			GR_PIPE_MODE_BUNDLE) {
+		*context = (bundle_value == GR_PIPE_MODE_MAJOR_COMPUTE);
+		nvgpu_log(g, gpu_dbg_mig, "(MIG) Bundle start "
+			"addr[%x] bundle_value[%x] is_compute_start[%d]",
+			bundle_addr, bundle_value, (*context != 0));
+		return *context != 0;
+	}
+
+	/* And now use context, only compute bundles allowed in MIG. */
+	if (*context == 0) {
+		nvgpu_log(g, gpu_dbg_mig, "(MIG) Skipped bundle "
+			"addr[%x] bundle_value[%x] ",
+			bundle_addr, bundle_value);
+		return false;
+	}
+
+	nvgpu_log(g, gpu_dbg_mig, "(MIG) Compute bundle "
+		"addr[%x] bundle_value[%x] ",
+		bundle_addr, bundle_value);
+
+	return true;
+}
+
 #ifndef CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION
 int gm20b_gr_init_load_sw_bundle_init(struct gk20a *g,
 		struct netlist_av_list *sw_bundle_init)
@@ -448,8 +485,16 @@ int gm20b_gr_init_load_sw_bundle_init(struct gk20a *g,
 	u32 i;
 	int err = 0;
 	u32 last_bundle_data = 0U;
+	int context = 0;
 
 	for (i = 0U; i < sw_bundle_init->count; i++) {
+		if (!g->ops.gr.init.is_allowed_sw_bundle(g,
+				sw_bundle_init->l[i].addr,
+				sw_bundle_init->l[i].value,
+				&context)) {
+			continue;
+		}
+
 		if (i == 0U || last_bundle_data != sw_bundle_init->l[i].value) {
 			nvgpu_writel(g, gr_pipe_bundle_data_r(),
 				sw_bundle_init->l[i].value);

drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c

@@ -810,9 +810,16 @@ int gv11b_gr_init_load_sw_veid_bundle(struct gk20a *g,
 	u32 i;
 	int err = 0;
 	u32 last_bundle_data = 0;
+	int context = 0;
 
 	for (i = 0U; i < sw_veid_bundle_init->count; i++) {
 		nvgpu_log_fn(g, "veid bundle count: %d", i);
+		if (!g->ops.gr.init.is_allowed_sw_bundle(g,
+				sw_veid_bundle_init->l[i].addr,
+				sw_veid_bundle_init->l[i].value,
+				&context)) {
+			continue;
+		}
 
 		if ((i == 0U) || (last_bundle_data !=
 					sw_veid_bundle_init->l[i].value)) {
@@ -942,8 +949,16 @@ int gv11b_gr_init_load_sw_bundle_init(struct gk20a *g,
 	int err = 0;
 	u32 last_bundle_data = 0U;
 	u32 bundle_data = 0;
+	int context = 0;
 
 	for (i = 0U; i < sw_bundle_init->count; i++) {
+		if (!g->ops.gr.init.is_allowed_sw_bundle(g,
+				sw_bundle_init->l[i].addr,
+				sw_bundle_init->l[i].value,
+				&context)) {
+			continue;
+		}
+
 		if ((i == 0U) || (last_bundle_data !=
 					sw_bundle_init->l[i].value)) {
 			bundle_data = sw_bundle_init->l[i].value;

drivers/gpu/nvgpu/hal/gr/init/gr_init_tu104.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -96,6 +96,47 @@ u32 tu104_gr_init_get_alpha_cb_default_size(struct gk20a *g)
 	return gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
 }
 
+static bool tu104_gr_init_is_allowed_sw_bundle64(struct gk20a *g,
+		u32 bundle_addr, u32 bundle_hi_value,
+		u32 bundle_lo_value, int *context)
+{
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_log(g, gpu_dbg_mig,
+			"Allowed bundle64 addr[%x] hi_value[%x] lo_value[%x] ",
+			bundle_addr, bundle_hi_value, bundle_lo_value);
+		return true;
+	}
+	/*
+	 * Capture whether the current bundle is compute or not.
+	 * Store in context.
+	 */
+	if (gr_pipe_bundle_address_value_v(bundle_addr) ==
+			GR_PIPE_MODE_BUNDLE) {
+		*context = ((bundle_hi_value == 0U) &&
+			(bundle_lo_value == GR_PIPE_MODE_MAJOR_COMPUTE));
+		nvgpu_log(g, gpu_dbg_mig, "(MIG) Bundle64 start "
+			"addr[%x] hi_value[%x] lo_value[%x] "
+				"is_compute_start[%d] ",
+			bundle_addr, bundle_hi_value, bundle_lo_value,
+			(*context != 0));
+		return *context != 0;
+	}
+
+	/* And now use context, only compute bundles allowed in MIG. */
+	if (*context == 0) {
+		nvgpu_log(g, gpu_dbg_mig, "(MIG) Skipped bundle "
+			"addr[%x] hi_value[%x] lo_value[%x] ",
+			bundle_addr, bundle_hi_value, bundle_lo_value);
+		return false;
+	}
+
+	nvgpu_log(g, gpu_dbg_mig, "(MIG) Compute bundle "
+		"addr[%x] hi_value[%x] lo_value[%x] ",
+		bundle_addr, bundle_hi_value, bundle_lo_value);
+
+	return true;
+}
+
 int tu104_gr_init_load_sw_bundle64(struct gk20a *g,
 		struct netlist_av64_list *sw_bundle64_init)
 {
@@ -103,8 +144,17 @@ int tu104_gr_init_load_sw_bundle64(struct gk20a *g,
 	u32 last_bundle_data_lo = 0;
 	u32 last_bundle_data_hi = 0;
 	int err = 0;
+	int context = 0;
 
 	for (i = 0U; i < sw_bundle64_init->count; i++) {
+		if (!tu104_gr_init_is_allowed_sw_bundle64(g,
+				sw_bundle64_init->l[i].addr,
+				sw_bundle64_init->l[i].value_hi,
+				sw_bundle64_init->l[i].value_lo,
+				&context)) {
+			continue;
+		}
+
 		if (i == 0U ||
 		   (last_bundle_data_lo != sw_bundle64_init->l[i].value_lo) ||
 		   (last_bundle_data_hi != sw_bundle64_init->l[i].value_hi)) {

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -440,6 +440,8 @@ static const struct gpu_ops gm20b_ops = {
 				gm20b_gr_init_get_supported_preemption_modes,
 			.get_default_preemption_modes =
 				gm20b_gr_init_get_default_preemption_modes,
+			.is_allowed_sw_bundle =
+				gm20b_gr_init_is_allowed_sw_bundle,
 #ifdef CONFIG_NVGPU_GRAPHICS
 			.rop_mapping = gm20b_gr_init_rop_mapping,
 			.get_gfxp_rtv_cb_size = NULL,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -513,6 +513,8 @@ static const struct gpu_ops gp10b_ops = {
 				gp10b_gr_init_get_supported_preemption_modes,
 			.get_default_preemption_modes =
 				gp10b_gr_init_get_default_preemption_modes,
+			.is_allowed_sw_bundle =
+				gm20b_gr_init_is_allowed_sw_bundle,
 #ifdef CONFIG_NVGPU_GRAPHICS
 			.get_ctx_attrib_cb_size =
 				gp10b_gr_init_get_ctx_attrib_cb_size,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -638,6 +638,8 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
 				gp10b_gr_init_get_supported_preemption_modes,
 			.get_default_preemption_modes =
 				gp10b_gr_init_get_default_preemption_modes,
+			.is_allowed_sw_bundle =
+				gm20b_gr_init_is_allowed_sw_bundle,
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 			.wait_initialized = nvgpu_gr_wait_initialized,
 #endif

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -677,6 +677,8 @@ static const struct gpu_ops tu104_ops = {
 				gp10b_gr_init_get_supported_preemption_modes,
 			.get_default_preemption_modes =
 				gp10b_gr_init_get_default_preemption_modes,
+			.is_allowed_sw_bundle =
+				gm20b_gr_init_is_allowed_sw_bundle,
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 			.wait_initialized = nvgpu_gr_wait_initialized,
 #endif

drivers/gpu/nvgpu/include/nvgpu/gops_gr.h

@@ -769,6 +769,8 @@ struct gops_gr_init {
 	 */
 	void (*wait_initialized)(struct gk20a *g);
 #endif
+	bool (*is_allowed_sw_bundle)(struct gk20a *g,
+			u32 bundle_addr, u32 bundle_value, int *context);
 #if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include "include/nvgpu/nvgpu_next_gops_gr_init.h"
 #endif