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gpu: nvgpu: doxygen for common.bus hals
Moved common.bus hals from gk20a.h to newly created file gops_bus.h. Added doxygen documentation for common.bus hal functions. JIRA NVGPU-2445 Change-Id: I45e5f5bbf3bd1cea2b895659a97661a2ea7998f4 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2223748 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
committed by
Alex Waterman
Alex Waterman
parent
49a620e48a
commit
4a1f49c6f8
@@ -6,7 +6,8 @@
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bus_fusa:
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safe: yes
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owner: Terje B
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sources: [ hal/bus/bus_gk20a_fusa.c,
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sources: [ include/nvgpu/gops_bus.h,
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hal/bus/bus_gk20a_fusa.c,
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hal/bus/bus_gk20a.h,
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hal/bus/bus_gm20b_fusa.c, hal/bus/bus_gm20b.h,
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hal/bus/bus_gp10b_fusa.c, hal/bus/bus_gp10b.h,
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@@ -35,6 +35,7 @@
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*
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* - @ref unit-ce
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* - @ref unit-mm
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* - @ref unit-common-bus
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* - @ref unit-fifo
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* - @ref unit-gr
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* - @ref unit-fb
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@@ -139,6 +140,7 @@ enum nvgpu_unit;
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#include <nvgpu/gops_ce.h>
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#include <nvgpu/gops_ptimer.h>
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#include <nvgpu/gops_top.h>
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#include <nvgpu/gops_bus.h>
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#include <nvgpu/gops_gr.h>
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#include <nvgpu/gops_falcon.h>
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#include <nvgpu/gops_fifo.h>
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@@ -578,20 +580,7 @@ struct gpu_ops {
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u32 (*get_litter_value)(struct gk20a *g, int value);
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int (*chip_init_gpu_characteristics)(struct gk20a *g);
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struct {
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int (*init_hw)(struct gk20a *g);
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void (*isr)(struct gk20a *g);
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int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
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int (*bar2_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
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#ifdef CONFIG_NVGPU_DGPU
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u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem,
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struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl,
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u32 w);
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#endif
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u32 (*read_sw_scratch)(struct gk20a *g, u32 index);
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void (*write_sw_scratch)(struct gk20a *g, u32 index, u32 val);
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void (*configure_debug_bus)(struct gk20a *g);
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} bus;
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struct gops_bus bus;
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struct gops_ptimer ptimer;
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133
drivers/gpu/nvgpu/include/nvgpu/gops_bus.h
Normal file
133
drivers/gpu/nvgpu/include/nvgpu/gops_bus.h
Normal file
@@ -0,0 +1,133 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GOPS_BUS_H
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#define NVGPU_GOPS_BUS_H
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#include <nvgpu/types.h>
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/**
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* @file
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*
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* common.bus interface.
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*/
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struct gk20a;
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/**
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*
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* This structure stores common.bus unit hal pointers.
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*
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* @see gpu_ops
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*/
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struct gops_bus {
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/**
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* @brief Initialize h/w access to gpu bus.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function enables interrupts for following errors:
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* NV_PBUS_INTR_EN_0_PRI_SQUASH - Error due to request sent to
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* while h/w block is in reset.
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* NV_PBUS_INTR_EN_0_PRI_FECSERR - Error due to fecs returning
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* error status from priv ring.
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* NV_PBUS_INTR_EN_0_PRI_TIMEOUT - Error due to request timing out.
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* This function also disables access to debug bus on safety build.
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*
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* @return 0 in case of success, < 0 in case of failure.
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*/
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int (*init_hw)(struct gk20a *g);
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/**
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* @brief ISR handler for gpu bus errors.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This functions handles interrupts related to generic gpu bus errors.
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* These interrupts are reported as host errors with following
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* description:
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* Bus Error Type |Host Error
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* :---------------------------:|:--------------------------:
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* SQUASH | GPU_HOST_PBUS_SQUASH_ERROR
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* FECSERR | GPU_HOST_PBUS_FECS_ERROR
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* TIMEOUT | GPU_HOST_PBUS_TIMEOUT_ERROR
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* FB_ACK_TIMEOUT | GPU_HOST_PBUS_TIMEOUT_ERROR
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* FB_ACK_EXTRA | GPU_HOST_PBUS_TIMEOUT_ERROR
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* FB_RDATA_TIMEOUT | GPU_HOST_PBUS_TIMEOUT_ERROR
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* FB_RDATA_EXTRA | GPU_HOST_PBUS_TIMEOUT_ERROR
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* POSTED_DEADLOCK_TIMEOUT | GPU_HOST_PBUS_TIMEOUT_ERROR
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* ACCESS_TIMEOUT | GPU_HOST_PBUS_TIMEOUT_ERROR
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*/
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void (*isr)(struct gk20a *g);
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/**
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* @brief Binds instance block address space for BAR1 memory access.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param bar1_inst [in] Instance memory to be used for
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* BAR1 access.
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*
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* BAR1 is generic memory to support sharing of data between h/w and
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* s/w. As a part of bar1 binding, bar1 is mapped to the virtual memory
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* space indicated by the instance block pointer and target memory
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* space. After programming bar1 block register, s/w will wait until
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* bar1 binding is done for maximum of 1000 retires with 5 usec delay
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* before each retry.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -EINVAL if h/w bar1 binding times out.
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* @retval -EINVAL if s/w init of nvgpu timer fails.
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*/
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int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
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/**
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* @brief Binds instance block address space for BAR2 memory access.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param bar2_inst [in] Instance memory to be used for
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* BAR2 access.
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*
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* BAR2 is virtual memory set-up done by s/w using system memory for
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* sharing of data between h/w and s/w, generally used for fault
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* buffers. As a part of bar2 binding, bar2 is mapped to the virtual
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* memory space ndicated by the instance block pointer and target
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* memory space. After programming bar2 block register, s/w will wait
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* until bar2 binding is done for maximum of 1000 retires with 5 usec
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* delay before each retry.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -EINVAL if h/w bar2 binding times out.
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* @retval -EINVAL if s/w init of nvgpu timer fails.
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*/
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int (*bar2_bind)(struct gk20a *g, struct nvgpu_mem *bar2_inst);
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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#ifdef CONFIG_NVGPU_DGPU
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u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem,
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struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w);
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#endif
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u32 (*read_sw_scratch)(struct gk20a *g, u32 index);
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void (*write_sw_scratch)(struct gk20a *g, u32 index, u32 val);
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void (*configure_debug_bus)(struct gk20a *g);
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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};
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#endif /* NVGPU_GOPS_BUS_H */
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