nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Split volt.h into private and public

Browse Source 
volt/volt*.h are used both by volt itself, and other units calling
into volt. Move all public dependencies to include/nvgpu/pmu/volt.h.

JIRA NVGPU-961

Change-Id: Ifad9ce7ff034d5fac73e0d40eec4d5e923d0fb99
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1986067
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-12-13 13:41:07 -08:00
committed by mobile promotions
parent 582d8192d9
commit 4ad7bc1c36
16 changed files with 100 additions and 68 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/clk/clk.c
View File

@@ -28,10 +28,10 @@
#include <nvgpu/bug.h>
#include <nvgpu/pmuif/ctrlperf.h>
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/volt.h>
#include "clk.h"
#include <nvgpu/timers.h>
#include "volt/volt.h"
#define BOOT_GPC2CLK_MHZ 2581U
#define BOOT_MCLK_MHZ 3003U

2
drivers/gpu/nvgpu/clk/clk_arb.c
View File

@@ -34,10 +34,10 @@
#include <nvgpu/timers.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/volt.h>
#include "clk/clk.h"
#include "lpwr/lpwr.h"
#include "volt/volt.h"
int nvgpu_clk_notification_queue_alloc(struct gk20a *g,
struct nvgpu_clk_notification_queue *queue,

3
drivers/gpu/nvgpu/common/pmu/pmu_fw.c
View File

@@ -31,12 +31,11 @@
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/volt.h>
#include "clk/clk.h"
#include "clk/clk_vin.h"
#include "clk/clk_fll.h"
#include "volt/volt.h"
#include "volt/volt_pmu.h"
/* PMU NS UCODE IMG */
#define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin"

2
drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
View File

@@ -36,10 +36,10 @@ struct gk20a;
#include <nvgpu/barrier.h>
#include <nvgpu/cond.h>
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/volt.h>
#include "clk/clk.h"
#include "lpwr/lpwr.h"
#include "volt/volt.h"
#define MAX_F_POINTS 256
#define DEFAULT_EVENT_NUMBER 32

84
drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h Normal file
View File

@@ -0,0 +1,84 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PMU_VOLT_H
#define NVGPU_PMU_VOLT_H
#include <nvgpu/types.h>
#include <nvgpu/boardobjgrp_e32.h>
struct gk20a;
/*!
* metadata of voltage rail functionality.
*/
struct voltage_rail_metadata {
u8 volt_domain_hal;
u8 pct_delta;
u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
u8 logic_rail_idx;
u8 sram_rail_idx;
struct boardobjgrp_e32 volt_rails;
};
struct voltage_device_metadata {
struct boardobjgrp_e32 volt_devices;
};
struct voltage_policy_metadata {
u8 perf_core_vf_seq_policy_idx;
struct boardobjgrp_e32 volt_policies;
};
struct obj_volt {
struct voltage_rail_metadata volt_rail_metadata;
struct voltage_device_metadata volt_dev_metadata;
struct voltage_policy_metadata volt_policy_metadata;
};
int nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv);
int nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g);
int nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv);
int nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g);
int volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv);
int volt_dev_sw_setup(struct gk20a *g);
int volt_dev_pmu_setup(struct gk20a *g);
int volt_rail_sw_setup(struct gk20a *g);
int volt_rail_pmu_setup(struct gk20a *g);
u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
int volt_policy_sw_setup(struct gk20a *g);
int volt_policy_pmu_setup(struct gk20a *g);
#endif /* NVGPU_PMU_VOLT_H */

2
drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c
View File

@@ -38,10 +38,10 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/enabled.h>
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/volt.h>
#include "clk/clk.h"
#include "lpwr/lpwr.h"
#include "volt/volt.h"
#ifdef CONFIG_DEBUG_FS
#include "os_linux.h"

2
drivers/gpu/nvgpu/pmu_perf/pmu_perf.h
View File

@@ -23,11 +23,11 @@
#define NVGPU_PERF_H
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "vfe_equ.h"
#include "vfe_var.h"
#include "volt/volt.h"
#include "lpwr/lpwr.h"
#include "change_seq.h"

19
drivers/gpu/nvgpu/volt/volt.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,20 +20,9 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_VOLT_H
#define NVGPU_VOLT_H
#include "volt_rail.h"
#include "volt_dev.h"
#include "volt_policy.h"
#include "volt_pmu.h"
#ifndef NVGPU_VOLT_VOLT_H
#define NVGPU_VOLT_VOLT_H
#define VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID 0xFF
struct obj_volt {
struct voltage_rail_metadata volt_rail_metadata;
struct voltage_device_metadata volt_dev_metadata;
struct voltage_policy_metadata volt_policy_metadata;
};
#endif /* NVGPU_VOLT_H */
#endif /* NVGPU_VOLT_VOLT_H */

2
drivers/gpu/nvgpu/volt/volt_dev.c
View File

@@ -35,6 +35,8 @@
#include "gp106/bios_gp106.h"
#include "volt.h"
#include "volt_dev.h"
#include "volt_rail.h"
#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0U
#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1U

7
drivers/gpu/nvgpu/volt/volt_dev.h
View File

@@ -50,10 +50,6 @@ struct voltage_device_entry {
u32 voltage_uv;
};
struct voltage_device_metadata {
struct boardobjgrp_e32 volt_devices;
};
/*!
* Extends VOLTAGE_DEVICE providing attributes specific to PWM controllers.
*/
@@ -71,7 +67,4 @@ struct voltage_device_pwm_entry {
};
/* PWM end */
int volt_dev_sw_setup(struct gk20a *g);
int volt_dev_pmu_setup(struct gk20a *g);
#endif /* NVGPU_VOLT_DEV_H */

2
drivers/gpu/nvgpu/volt/volt_pmu.c
View File

@@ -33,6 +33,8 @@
#include "gp106/bios_gp106.h"
#include "volt.h"
#include "volt_rail.h"
#include "volt_pmu.h"
#define RAIL_COUNT_GP 2
#define RAIL_COUNT_GV 1

16
drivers/gpu/nvgpu/volt/volt_pmu.h
View File

@@ -24,23 +24,7 @@
#define NVGPU_VOLT_PMU_H
u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g);
int volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv);
int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv);
int nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g);
int nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv);
int nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g);
#endif /* NVGPU_VOLT_PMU_H */

1
drivers/gpu/nvgpu/volt/volt_policy.c
View File

@@ -31,6 +31,7 @@
#include "gp106/bios_gp106.h"
#include "volt.h"
#include "volt_policy.h"
static int volt_policy_pmu_data_init_super(struct gk20a *g,
struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata)

7
drivers/gpu/nvgpu/volt/volt_policy.h
View File

@@ -35,11 +35,6 @@ struct voltage_policy {
struct boardobj super;
};
struct voltage_policy_metadata {
u8 perf_core_vf_seq_policy_idx;
struct boardobjgrp_e32 volt_policies;
};
/*!
* extends voltage_policy providing attributes
* common to all voltage_policy_split_rail.
@@ -75,6 +70,4 @@ struct voltage_policy_single_rail_multi_step {
u32 ramp_down_step_size_uv;
};
int volt_policy_sw_setup(struct gk20a *g);
int volt_policy_pmu_setup(struct gk20a *g);
#endif /* NVGPU_VOLT_POLICY_H */

1
drivers/gpu/nvgpu/volt/volt_rail.c
View File

@@ -31,6 +31,7 @@
#include "gp106/bios_gp106.h"
#include "volt.h"
#include "volt_rail.h"
u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
{

16
drivers/gpu/nvgpu/volt/volt_rail.h
View File

@@ -65,26 +65,10 @@ struct voltage_rail {
s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
};
/*!
* metadata of voltage rail functionality.
*/
struct voltage_rail_metadata {
u8 volt_domain_hal;
u8 pct_delta;
u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
u8 logic_rail_idx;
u8 sram_rail_idx;
struct boardobjgrp_e32 volt_rails;
};
u8 volt_rail_vbios_volt_domain_convert_to_internal
(struct gk20a *g, u8 vbios_volt_domain);
int volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
*pvolt_rail, u8 volt_dev_idx, u8 operation_type);
u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
int volt_rail_sw_setup(struct gk20a *g);
int volt_rail_pmu_setup(struct gk20a *g);
#endif /* NVGPU_VOLT_RAIL_H */