gpu: nvgpu: add fifo.bar1_snooping_disable hal

Add fifo.bar1_snooping_disable hal

Rename and move from fifo_gk20a.c to fifo.c
gk20a_fifo_suspend -> nvgpu_fifo_suspend

Rename
gk20a_readl -> nvgpu_readl
gk20a_writel -> nvgpu_writel

Remove unused defines and function prototypes
from fifo_gk20a.h

JIRA NVGPU-2012

Change-Id: If7eed93340c5c60802b1af40790482fd5e1b33c1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109007
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/fifo.c

@@ -280,3 +280,19 @@ const char *nvgpu_fifo_decode_pbdma_ch_eng_status(u32 index)
 		return pbdma_ch_eng_status_str[index];
 	}
 }
+
+int nvgpu_fifo_suspend(struct gk20a *g)
+{
+	nvgpu_log_fn(g, " ");
+
+	if (g->ops.mm.is_bar1_supported(g)) {
+		g->ops.fifo.bar1_snooping_disable(g);
+	}
+
+	/* disable fifo intr */
+	g->ops.fifo.intr_0_enable(g, false);
+	g->ops.fifo.intr_1_enable(g, false);
+
+	nvgpu_log_fn(g, "done");
+	return 0;
+}

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -118,7 +118,7 @@ int gk20a_prepare_poweroff(struct gk20a *g)
 	if ((tmp_ret != 0) && (ret == 0)) {
 		ret = tmp_ret;
 	}
-	tmp_ret = gk20a_fifo_suspend(g);
+	tmp_ret = nvgpu_fifo_suspend(g);
 	if ((tmp_ret != 0) && (ret == 0)) {
 		ret = tmp_ret;
 	}

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -439,6 +439,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 			gp10b_fifo_get_mmu_fault_client_desc,
 		.get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc,
 		.is_mmu_fault_pending = NULL,
+		.bar1_snooping_disable = gk20a_fifo_bar1_snooping_disable,
 	},
 	.engine = {
 		.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -47,11 +47,11 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
 
 	nvgpu_cg_blcg_fifo_load_enable(g);
 
-	timeout = gk20a_readl(g, fifo_fb_timeout_r());
+	timeout = nvgpu_readl(g, fifo_fb_timeout_r());
 	timeout = set_field(timeout, fifo_fb_timeout_period_m(),
 			fifo_fb_timeout_period_max_f());
 	nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout);
-	gk20a_writel(g, fifo_fb_timeout_r(), timeout);
+	nvgpu_writel(g, fifo_fb_timeout_r(), timeout);
 
 	g->ops.pbdma.setup_hw(g);
 
@@ -73,10 +73,10 @@ int gk20a_init_fifo_setup_hw(struct gk20a *g)
 	/* set the base for the userd region now */
 	shifted_addr = f->userd_gpu_va >> 12;
 	if ((shifted_addr >> 32) != 0U) {
-		nvgpu_err(g, "GPU VA > 32 bits %016llx\n", f->userd_gpu_va);
+		nvgpu_err(g, "GPU VA > 32 bits %016llx", f->userd_gpu_va);
 		return -EFAULT;
 	}
-	gk20a_writel(g, fifo_bar1_base_r(),
+	nvgpu_writel(g, fifo_bar1_base_r(),
 			fifo_bar1_base_ptr_f(u64_lo32(shifted_addr)) |
 			fifo_bar1_base_valid_true_f());
 
@@ -85,30 +85,18 @@ int gk20a_init_fifo_setup_hw(struct gk20a *g)
 	return 0;
 }
 
-int gk20a_fifo_suspend(struct gk20a *g)
+void gk20a_fifo_bar1_snooping_disable(struct gk20a *g)
 {
-	nvgpu_log_fn(g, " ");
-
-	/* stop bar1 snooping */
-	if (g->ops.mm.is_bar1_supported(g)) {
-		gk20a_writel(g, fifo_bar1_base_r(),
-			fifo_bar1_base_valid_false_f());
-	}
-
-	/* disable fifo intr */
-	g->ops.fifo.intr_0_enable(g, false);
-	g->ops.fifo.intr_1_enable(g, false);
-
-	nvgpu_log_fn(g, "done");
-	return 0;
+	nvgpu_writel(g, fifo_bar1_base_r(),
+		fifo_bar1_base_valid_false_f());
 }
 
 int gk20a_fifo_init_pbdma_map(struct gk20a *g, u32 *pbdma_map, u32 num_pbdma)
 {
 	u32 id;
 
-	for (id = 0; id < num_pbdma; ++id) {
-		pbdma_map[id] = gk20a_readl(g, fifo_pbdma_map_r(id));
+	for (id = 0U; id < num_pbdma; ++id) {
+		pbdma_map[id] = nvgpu_readl(g, fifo_pbdma_map_r(id));
 	}
 
 	return 0;

drivers/gpu/nvgpu/gk20a/fifo_gk20a.h

@@ -24,6 +24,7 @@
 #ifndef FIFO_GK20A_H
 #define FIFO_GK20A_H
 
+#include <nvgpu/types.h>
 #include <nvgpu/kref.h>
 #include <nvgpu/fifo.h>
 #include <nvgpu/engines.h>
@@ -42,9 +43,6 @@ struct tsg_gk20a;
 #define FIFO_INVAL_RUNLIST_ID		(~U32(0U))
 #define FIFO_INVAL_SYNCPT_ID		(~U32(0U))
 
-#define RC_YES				1U
-#define RC_NO				0U
-
 /*
  * Number of entries in the kickoff latency buffer, used to calculate
  * the profiling and histogram. This number is calculated to be statistically
@@ -200,16 +198,12 @@ struct fifo_gk20a {
 	u32 channel_base;
 };
 
-int gk20a_init_fifo_setup_hw(struct gk20a *g);
-
-u32 gk20a_fifo_engines_on_ch(struct gk20a *g, u32 chid);
-
-int gk20a_fifo_suspend(struct gk20a *g);
-
 int gk20a_init_fifo_reset_enable_hw(struct gk20a *g);
-
-void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g,
-		unsigned long fault_id);
+int gk20a_init_fifo_setup_hw(struct gk20a *g);
+void gk20a_fifo_bar1_snooping_disable(struct gk20a *g);
+int gk20a_fifo_init_pbdma_map(struct gk20a *g, u32 *pbdma_map, u32 num_pbdma);
+u32 gk20a_fifo_get_runlist_timeslice(struct gk20a *g);
+u32 gk20a_fifo_get_pb_timeslice(struct gk20a *g);
 
 #ifdef CONFIG_DEBUG_FS
 struct fifo_profile_gk20a *gk20a_fifo_profile_acquire(struct gk20a *g);
@@ -232,8 +226,4 @@ static inline void gk20a_fifo_profile_snapshot(
 }
 #endif
 
-int gk20a_fifo_init_pbdma_map(struct gk20a *g, u32 *pbdma_map, u32 num_pbdma);
-u32 gk20a_fifo_get_runlist_timeslice(struct gk20a *g);
-u32 gk20a_fifo_get_pb_timeslice(struct gk20a *g);
-
 #endif /* FIFO_GK20A_H */

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -584,6 +584,7 @@ static const struct gpu_ops gm20b_ops = {
 		.get_runlist_timeslice = gk20a_fifo_get_runlist_timeslice,
 		.get_pb_timeslice = gk20a_fifo_get_pb_timeslice,
 		.is_mmu_fault_pending = gk20a_fifo_is_mmu_fault_pending,
+		.bar1_snooping_disable = gk20a_fifo_bar1_snooping_disable,
 	},
 	.engine = {
 		.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -648,6 +648,7 @@ static const struct gpu_ops gp10b_ops = {
 		.get_runlist_timeslice = gk20a_fifo_get_runlist_timeslice,
 		.get_pb_timeslice = gk20a_fifo_get_pb_timeslice,
 		.is_mmu_fault_pending = gk20a_fifo_is_mmu_fault_pending,
+		.bar1_snooping_disable = gk20a_fifo_bar1_snooping_disable,
 	},
 	.engine = {
 		.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,

drivers/gpu/nvgpu/include/nvgpu/fifo.h

@@ -25,6 +25,8 @@
 #ifndef NVGPU_FIFO_COMMON_H
 #define NVGPU_FIFO_COMMON_H
 
+#include <nvgpu/types.h>
+
 #define ID_TYPE_CHANNEL			0U
 #define ID_TYPE_TSG			1U
 #define ID_TYPE_UNKNOWN			(~U32(0U))
@@ -46,5 +48,6 @@ void nvgpu_fifo_cleanup_sw(struct gk20a *g);
 void nvgpu_fifo_cleanup_sw_common(struct gk20a *g);
 
 const char *nvgpu_fifo_decode_pbdma_ch_eng_status(u32 index);
+int nvgpu_fifo_suspend(struct gk20a *g);
 
 #endif /* NVGPU_FIFO_COMMON_H */

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1030,6 +1030,7 @@ struct gpu_ops {
 		bool (*is_mmu_fault_pending)(struct gk20a *g);
 		u32  (*mmu_fault_id_to_pbdma_id)(struct gk20a *g,
 					u32 mmu_fault_id);
+		void (*bar1_snooping_disable)(struct gk20a *g);
 
 	} fifo;
 	struct {