gpu: nvgpu: Reorg fb HAL initialization

Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
fb sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I3fdbf6059ef664caf8d33797a8a5f3f8eb6485bf
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537748
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gv100/fb_gv100.c

@@ -21,7 +21,6 @@
 #include <nvgpu/gmmu.h>
 
 #include "gk20a/gk20a.h"
-#include "gv11b/fb_gv11b.h"
 #include "gv100/fb_gv100.h"
 
 #include <nvgpu/hw/gv100/hw_fb_gv100.h>
@@ -29,7 +28,7 @@
 #define HW_SCRUB_TIMEOUT_DEFAULT	100 /* usec */
 #define HW_SCRUB_TIMEOUT_MAX		2000000 /* usec */
 
-static void gv100_fb_reset(struct gk20a *g)
+void gv100_fb_reset(struct gk20a *g)
 {
 	u32 val;
 	int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT;
@@ -50,9 +49,3 @@ static void gv100_fb_reset(struct gk20a *g)
 	val &= ~fb_mmu_priv_level_mask_write_violation_m();
 	gk20a_writel(g, fb_mmu_priv_level_mask_r(), val);
 }
-
-void gv100_init_fb(struct gpu_ops *gops)
-{
-	gv11b_init_fb(gops);
-	gops->fb.reset = gv100_fb_reset;
-}

drivers/gpu/nvgpu/gv100/fb_gv100.h

@@ -16,7 +16,7 @@
 #ifndef _NVGPU_GV100_FB
 #define _NVGPU_GV100_FB
 
-struct gpu_ops;
+struct gk20a;
 
-void gv100_init_fb(struct gpu_ops *gops);
+void gv100_fb_reset(struct gk20a *g);
 #endif

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -30,10 +30,14 @@
 #include "gk20a/pramin_gk20a.h"
 #include "gk20a/flcn_gk20a.h"
 #include "gk20a/regops_gk20a.h"
+#include "gk20a/fb_gk20a.h"
 
 #include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
+#include "gm20b/fb_gm20b.h"
+
+#include "gp10b/fb_gp10b.h"
 
 #include "gp106/clk_gp106.h"
 #include "gp106/clk_arb_gp106.h"
@@ -61,7 +65,7 @@
 #include "gv100/gr_ctx_gv100.h"
 #include "gv100/mm_gv100.h"
 #include "gv11b/pmu_gv11b.h"
-#include "gv100/fb_gv100.h"
+#include "gv11b/fb_gv11b.h"
 #include "gv11b/fifo_gv11b.h"
 #include "gv11b/gv11b_gating_reglist.h"
 #include "gv11b/regops_gv11b.h"
@@ -69,6 +73,7 @@
 
 #include "gv100.h"
 #include "hal_gv100.h"
+#include "gv100/fb_gv100.h"
 
 #include <nvgpu/debug.h>
 #include <nvgpu/enabled.h>
@@ -200,6 +205,23 @@ static const struct gpu_ops gv100_ops = {
 		.isr_nonstall = gp10b_ce_nonstall_isr,
 		.get_num_pce = gv11b_ce_get_num_pce,
 	},
+	.fb = {
+		.reset = gv100_fb_reset,
+		.init_hw = gk20a_fb_init_hw,
+		.init_fs_state = gv11b_fb_init_fs_state,
+		.init_cbc = gv11b_fb_init_cbc,
+		.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
+		.set_use_full_comp_tag_line =
+			gm20b_fb_set_use_full_comp_tag_line,
+		.compression_page_size = gp10b_fb_compression_page_size,
+		.compressible_page_size = gp10b_fb_compressible_page_size,
+		.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
+		.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
+		.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
+		.set_debug_mode = gm20b_fb_set_debug_mode,
+		.tlb_invalidate = gk20a_fb_tlb_invalidate,
+		.hub_isr = gv11b_fb_hub_isr,
+	},
 	.fifo = {
 		.init_fifo_setup_hw = gv11b_init_fifo_setup_hw,
 		.bind_channel = channel_gm20b_bind,
@@ -424,10 +446,12 @@ int gv100_init_hal(struct gk20a *g)
 	g->bootstrap_owner = LSF_FALCON_ID_SEC2;
 
 	gv11b_init_gr(g);
-	gv100_init_fb(gops);
 	gv100_init_mm(gops);
 	gp106_init_pmu_ops(g);
 
+	gv11b_init_uncompressed_kind_map();
+	gv11b_init_kind_attr();
+
 	g->name = "gv10x";
 
 	c->twod_class = FERMI_TWOD_A;

drivers/gpu/nvgpu/gv11b/fb_gv11b.c

@@ -75,7 +75,7 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
 
 }
 
-static void gv11b_fb_init_fs_state(struct gk20a *g)
+void gv11b_fb_init_fs_state(struct gk20a *g)
 {
 	nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb");
 
@@ -87,7 +87,7 @@ static void gv11b_fb_init_fs_state(struct gk20a *g)
 			gk20a_readl(g, fb_mmu_num_active_ltcs_r())));
 }
 
-static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
+void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
 {
 	u32 max_size = gr->max_comptag_mem;
 	/* one tag line covers 64KB */
@@ -137,7 +137,7 @@ static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
 
 }
 
-static void gv11b_fb_reset(struct gk20a *g)
+void gv11b_fb_reset(struct gk20a *g)
 {
 	u32 val;
 
@@ -251,7 +251,7 @@ static const char *const gpc_client_descs_gv11b[] = {
 	"t1 36", "t1 37", "t1 38", "t1 39",
 };
 
-static noinline_for_stack void gv11b_init_uncompressed_kind_map(void)
+noinline_for_stack void gv11b_init_uncompressed_kind_map(void)
 {
 	int i;
 
@@ -672,7 +672,7 @@ static noinline_for_stack bool gv11b_kind_zbc(u8 k)
 			k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v());
 }
 
-static void gv11b_init_kind_attr(void)
+void gv11b_init_kind_attr(void)
 {
 	u16 k;
 
@@ -1815,7 +1815,7 @@ static void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr)
 				fb_mmu_fault_status_valid_clear_f());
 }
 
-static void gv11b_fb_hub_isr(struct gk20a *g)
+void gv11b_fb_hub_isr(struct gk20a *g)
 {
 	u32 status, niso_intr;
 
@@ -1967,16 +1967,3 @@ static int gv11b_fb_fix_page_fault(struct gk20a *g,
 			pte[1], pte[0]);
 	return err;
 }
-
-void gv11b_init_fb(struct gpu_ops *gops)
-{
-	gp10b_init_fb(gops);
-	gops->fb.hub_isr = gv11b_fb_hub_isr;
-	gops->fb.reset = gv11b_fb_reset;
-	gops->fb.init_fs_state = gv11b_fb_init_fs_state;
-	gops->fb.init_cbc = gv11b_fb_init_cbc;
-
-	gv11b_init_uncompressed_kind_map();
-	gv11b_init_kind_attr();
-
-}

drivers/gpu/nvgpu/gv11b/fb_gv11b.h

@@ -42,9 +42,13 @@
 #define	FAULT_TYPE_OTHER_AND_NONREPLAY		0
 #define	FAULT_TYPE_REPLAY			1
 
-struct gpu_ops;
+struct gk20a;
+
+void gv11b_fb_init_fs_state(struct gk20a *g);
+void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr);
+void gv11b_fb_reset(struct gk20a *g);
+void gv11b_fb_hub_isr(struct gk20a *g);
 
-void gv11b_init_fb(struct gpu_ops *gops);
 u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g,
 				 unsigned int index);
 void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g,
@@ -56,4 +60,7 @@ void gv11b_fb_disable_hub_intr(struct gk20a *g,
 	 unsigned int index, unsigned int intr_type);
 void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index);
 bool gv11b_fb_mmu_fault_pending(struct gk20a *g);
+
+noinline_for_stack void gv11b_init_uncompressed_kind_map(void);
+void gv11b_init_kind_attr(void);
 #endif

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -29,9 +29,11 @@
 #include "gk20a/bus_gk20a.h"
 #include "gk20a/flcn_gk20a.h"
 #include "gk20a/regops_gk20a.h"
+#include "gk20a/fb_gk20a.h"
 
 #include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
+#include "gm20b/fb_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
 
 #include "gp10b/ltc_gp10b.h"
@@ -41,6 +43,7 @@
 #include "gp10b/priv_ring_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
 #include "gp10b/fecs_trace_gp10b.h"
+#include "gp10b/fb_gp10b.h"
 
 #include "hal_gv11b.h"
 #include "gr_gv11b.h"
@@ -178,6 +181,23 @@ static const struct gpu_ops gv11b_ops = {
 		.isr_nonstall = gp10b_ce_nonstall_isr,
 		.get_num_pce = gv11b_ce_get_num_pce,
 	},
+	.fb = {
+		.reset = gv11b_fb_reset,
+		.init_hw = gk20a_fb_init_hw,
+		.init_fs_state = gv11b_fb_init_fs_state,
+		.init_cbc = gv11b_fb_init_cbc,
+		.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
+		.set_use_full_comp_tag_line =
+			gm20b_fb_set_use_full_comp_tag_line,
+		.compression_page_size = gp10b_fb_compression_page_size,
+		.compressible_page_size = gp10b_fb_compressible_page_size,
+		.vpr_info_fetch = gm20b_fb_vpr_info_fetch,
+		.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
+		.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
+		.set_debug_mode = gm20b_fb_set_debug_mode,
+		.tlb_invalidate = gk20a_fb_tlb_invalidate,
+		.hub_isr = gv11b_fb_hub_isr,
+	},
 	.clock_gating = {
 		.slcg_bus_load_gating_prod =
 			gv11b_slcg_bus_load_gating_prod,
@@ -408,6 +428,7 @@ int gv11b_init_hal(struct gk20a *g)
 
 	gops->ltc = gv11b_ops.ltc;
 	gops->ce2 = gv11b_ops.ce2;
+	gops->fb = gv11b_ops.fb;
 	gops->clock_gating = gv11b_ops.clock_gating;
 	gops->fifo = gv11b_ops.fifo;
 	gops->gr_ctx = gv11b_ops.gr_ctx;
@@ -435,10 +456,12 @@ int gv11b_init_hal(struct gk20a *g)
 	__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
 
 	gv11b_init_gr(g);
-	gv11b_init_fb(gops);
 	gv11b_init_mm(gops);
 	gv11b_init_pmu_ops(g);
 
+	gv11b_init_uncompressed_kind_map();
+	gv11b_init_kind_attr();
+
 	g->name = "gv11b";
 
 	c->twod_class = FERMI_TWOD_A;