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gpu: nvgpu: Return Nominal clocks when PSTATE is Disabled

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When NVGPU_PMU_PSTATE is disabled, dGPU will boot with Initialization
state --> nominal clocks from VBIOS.
Use this values in clk_maxrate when PSTATE is disabled.

Bug 200533299

Change-Id: I0861495999803f5876c5865f33c494ee8de6d2e0
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2149444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2019-07-08 14:44:05 +05:30
committed by mobile promotions
parent 8682c56531
commit 4c0412ad18
2 changed files with 15 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/nvgpu/hal/clk/clk_gv100.c
View File

@@ -56,6 +56,7 @@
#define XTAL_SCALE_TO_KHZ 1
#define NUM_NAMEMAPS (3U)
#define XTAL4X_KHZ 108000
#define BOOT_GPCCLK_MHZ 645U
u32 gv100_crystal_clk_hz(struct gk20a *g)
{
@@ -238,14 +239,20 @@ void gv100_suspend_clk_support(struct gk20a *g)
unsigned long gv100_clk_maxrate(struct gk20a *g, u32 api_domain)
{
u16 min_mhz, max_mhz;
u16 min_mhz = 0, max_mhz = 0;
int status;
status = nvgpu_clk_arb_get_arbiter_clk_range(g, api_domain, &min_mhz,
&max_mhz);
if (status != 0) {
nvgpu_err(g, "failed to fetch clock range");
return 0U;
if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
status = nvgpu_clk_arb_get_arbiter_clk_range(g, api_domain,
&min_mhz, &max_mhz);
if (status != 0) {
nvgpu_err(g, "failed to fetch clock range");
return 0U;
}
} else {
if (api_domain == NVGPU_CLK_DOMAIN_GPCCLK) {
max_mhz = BOOT_GPCCLK_MHZ;
}
}
return (max_mhz * 1000UL * 1000UL);

4
drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
View File

@@ -107,9 +107,9 @@ struct nvgpu_clk_session;
* defines in uapi header
*/
/* Memory clock */
#define NVGPU_CLK_DOMAIN_MCLK (0)
#define NVGPU_CLK_DOMAIN_MCLK 0U
/* Main graphics core clock */
#define NVGPU_CLK_DOMAIN_GPCCLK (1)
#define NVGPU_CLK_DOMAIN_GPCCLK 1U
#define NVGPU_CLK_DOMAIN_MAX (NVGPU_CLK_DOMAIN_GPCCLK)