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gpu: nvgpu: update pwm source enum & VFE entry
JIRA DNVGPU-123 Change-Id: Ia28db5d645aa431f11dc8720bf1d08e6d756e20f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1227670 (cherry picked from commit 2c7f89ceef3f9173fefa44b1a959345744e66536) Reviewed-on: http://git-master/r/1244659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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@@ -26,6 +26,7 @@
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#define CTRL_VOLT_DOMAIN_INVALID 0x00
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#define CTRL_VOLT_DOMAIN_LOGIC 0x01
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#define CLK_PROG_VFE_ENTRY_LOGIC 0x00
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#define CLK_PROG_VFE_ENTRY_SRAM 0x01
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/*
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* Macros for Voltage Domain HAL.
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@@ -60,7 +61,8 @@
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enum nv_pmu_pmgr_pwm_source {
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NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
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NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1 = 5,
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NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
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NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1,
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NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7,
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NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8,
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};
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@@ -624,6 +624,7 @@ struct gpu_ops {
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void (*disable_slowboot)(struct gk20a *g);
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int (*init_clk_support)(struct gk20a *g);
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int (*suspend_clk_support)(struct gk20a *g);
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u32 (*get_crystal_clk_hz)(struct gk20a *g);
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} clk;
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bool privsecurity;
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bool securegpccs;
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