gpu: nvgpu: update pwm source enum & VFE entry

JIRA DNVGPU-123

Change-Id: Ia28db5d645aa431f11dc8720bf1d08e6d756e20f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1227670
(cherry picked from commit 2c7f89ceef3f9173fefa44b1a959345744e66536)
Reviewed-on: http://git-master/r/1244659
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2016-09-27 16:40:12 +05:30
committed by mobile promotions
parent cc438a3609
commit 4c2e65c60b
2 changed files with 4 additions and 1 deletions

View File

@@ -26,6 +26,7 @@
#define CTRL_VOLT_DOMAIN_INVALID 0x00
#define CTRL_VOLT_DOMAIN_LOGIC 0x01
#define CLK_PROG_VFE_ENTRY_LOGIC 0x00
#define CLK_PROG_VFE_ENTRY_SRAM 0x01
/*
* Macros for Voltage Domain HAL.
@@ -60,7 +61,8 @@
enum nv_pmu_pmgr_pwm_source {
NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1 = 5,
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1,
NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7,
NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8,
};

View File

@@ -624,6 +624,7 @@ struct gpu_ops {
void (*disable_slowboot)(struct gk20a *g);
int (*init_clk_support)(struct gk20a *g);
int (*suspend_clk_support)(struct gk20a *g);
u32 (*get_crystal_clk_hz)(struct gk20a *g);
} clk;
bool privsecurity;
bool securegpccs;