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gpu: nvgpu: move runlist HALs to hal/fifo

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Move runlists HALs to hal/fifo.
Update makefiles and include directives.

Renamed
- gk20a_readl -> nvgpu_readl
- gk20a_writel -> nvgpu_writel

Jira NVGPU-1988

Change-Id: Ia8f9f50d42f0863c522a0d2caca0b9c775be597a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092749
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-04-08 13:52:54 -07:00
committed by mobile promotions
parent 8e9ec4f1b7
commit 4c84bf54ff
18 changed files with 42 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/Makefile
View File

@@ -251,6 +251,10 @@ nvgpu-y += \
hal/fifo/ramin_gm20b.o \
hal/fifo/ramin_gp10b.o \
hal/fifo/ramin_gv11b.o \
hal/fifo/runlist_gk20a.o \
hal/fifo/runlist_gv11b.o \
hal/fifo/runlist_gv100.o \
hal/fifo/runlist_tu104.o \
hal/fifo/tsg_gk20a.o \
hal/fifo/tsg_gv11b.o \
hal/fifo/userd_gk20a.o \
@@ -468,10 +472,6 @@ nvgpu-y += \
common/fifo/submit.o \
common/fifo/tsg.o \
common/fifo/runlist.o \
common/fifo/runlist_gk20a.o \
common/fifo/runlist_gv11b.o \
common/fifo/runlist_gv100.o \
common/fifo/runlist_tu104.o \
common/fifo/channel_gk20a.o \
common/fifo/channel_gm20b.o \
common/fifo/channel_gv11b.o \

8
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -182,10 +182,6 @@ srcs += common/sim.c \
common/fifo/submit.c \
common/fifo/tsg.c \
common/fifo/runlist.c \
common/fifo/runlist_gk20a.c \
common/fifo/runlist_gv11b.c \
common/fifo/runlist_gv100.c \
common/fifo/runlist_tu104.c \
common/fifo/channel_gk20a.c \
common/fifo/channel_gm20b.c \
common/fifo/channel_gv11b.c \
@@ -383,6 +379,10 @@ srcs += common/sim.c \
hal/fifo/ramin_gm20b.c \
hal/fifo/ramin_gp10b.c \
hal/fifo/ramin_gv11b.c \
hal/fifo/runlist_gk20a.c \
hal/fifo/runlist_gv11b.c \
hal/fifo/runlist_gv100.c \
hal/fifo/runlist_tu104.c \
hal/fifo/tsg_gk20a.c \
hal/fifo/tsg_gv11b.c \
hal/fifo/userd_gk20a.c \

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -28,6 +28,7 @@
#include "hal/fifo/ramin_gk20a.h"
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/ramin_gp10b.h"
#include "hal/fifo/runlist_gk20a.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/mmu_fault_gm20b.h"
#include "hal/fifo/mmu_fault_gp10b.h"
@@ -47,7 +48,6 @@
#include "common/perf/perf_gm20b.h"
#include "common/regops/regops_gp10b.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/channel_gm20b.h"
#include "common/clk_arb/clk_arb_gp10b.h"

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -30,6 +30,7 @@
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/ramin_gp10b.h"
#include "hal/fifo/ramin_gv11b.h"
#include "hal/fifo/runlist_gv11b.h"
#include "hal/fifo/tsg_gv11b.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/userd_gv11b.h"
@@ -62,7 +63,6 @@
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_gv11b.h"
#include "common/fifo/runlist_gv11b.h"
#include "common/fifo/channel_gv11b.h"
#include "common/clk_arb/clk_arb_gp10b.h"

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -62,6 +62,7 @@
#include "hal/fifo/ramfc_gk20a.h"
#include "hal/fifo/ramin_gk20a.h"
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/runlist_gk20a.h"
#include "hal/fifo/tsg_gk20a.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/fifo_intr_gk20a.h"
@@ -87,7 +88,6 @@
#include "common/sync/syncpt_cmdbuf_gk20a.h"
#include "common/sync/sema_cmdbuf_gk20a.h"
#include "common/regops/regops_gm20b.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/channel_gk20a.h"
#include "common/fifo/channel_gm20b.h"

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -75,6 +75,7 @@
#include "hal/fifo/ramin_gk20a.h"
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/ramin_gp10b.h"
#include "hal/fifo/runlist_gk20a.h"
#include "hal/fifo/tsg_gk20a.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/fifo_intr_gk20a.h"
@@ -109,7 +110,6 @@
#include "common/sync/syncpt_cmdbuf_gk20a.h"
#include "common/sync/sema_cmdbuf_gk20a.h"
#include "common/regops/regops_gp10b.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/channel_gk20a.h"
#include "common/fifo/channel_gm20b.h"
#include "common/clk_arb/clk_arb_gp10b.h"

6
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -65,6 +65,9 @@
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/ramin_gp10b.h"
#include "hal/fifo/ramin_gv11b.h"
#include "hal/fifo/runlist_gk20a.h"
#include "hal/fifo/runlist_gv11b.h"
#include "hal/fifo/runlist_gv100.h"
#include "hal/fifo/tsg_gv11b.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/userd_gv11b.h"
@@ -120,9 +123,6 @@
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_gv100.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/runlist_gv11b.h"
#include "common/fifo/runlist_gv100.h"
#include "common/fifo/channel_gk20a.h"
#include "common/fifo/channel_gm20b.h"
#include "common/fifo/channel_gv11b.h"

4
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -67,6 +67,8 @@
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/ramin_gp10b.h"
#include "hal/fifo/ramin_gv11b.h"
#include "hal/fifo/runlist_gk20a.h"
#include "hal/fifo/runlist_gv11b.h"
#include "hal/fifo/tsg_gv11b.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/userd_gv11b.h"
@@ -110,8 +112,6 @@
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_gv11b.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/runlist_gv11b.h"
#include "common/fifo/channel_gk20a.h"
#include "common/fifo/channel_gm20b.h"
#include "common/fifo/channel_gv11b.h"

21
drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c → drivers/gpu/nvgpu/hal/fifo/runlist_gk20a.c
View File

@@ -35,7 +35,6 @@
#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
#define FECS_METHOD_WFI_RESTORE 0x80000U
#define FECS_MAILBOX_0_ACK_RESTORE 0x4U
int gk20a_runlist_reschedule(struct channel_gk20a *ch, bool preempt_next)
@@ -65,12 +64,12 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
return ret;
}
if (wait_preempt && ((gk20a_readl(g, fifo_preempt_r()) &
if (wait_preempt && ((nvgpu_readl(g, fifo_preempt_r()) &
fifo_preempt_pending_true_f()) != 0U)) {
return ret;
}
fecsstat0 = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0));
fecsstat0 = nvgpu_readl(g, gr_fecs_ctxsw_mailbox_r(0));
g->ops.engine_status.read_engine_status_info(g, gr_eng_id, &engine_status);
if (nvgpu_engine_status_is_ctxsw_switch(&engine_status)) {
nvgpu_engine_status_get_next_ctx_id_type(&engine_status,
@@ -81,7 +80,7 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
if ((preempt_id == ch->tsgid) && (preempt_type != 0U)) {
return ret;
}
fecsstat1 = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0));
fecsstat1 = nvgpu_readl(g, gr_fecs_ctxsw_mailbox_r(0));
if (fecsstat0 != FECS_MAILBOX_0_ACK_RESTORE ||
fecsstat1 != FECS_MAILBOX_0_ACK_RESTORE) {
/* preempt useless if FECS acked save and started restore */
@@ -92,8 +91,8 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
#ifdef TRACEPOINTS_ENABLED
trace_gk20a_reschedule_preempt_next(ch->chid, fecsstat0,
engine_status.reg_data,
fecsstat1, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)),
gk20a_readl(g, fifo_preempt_r()));
fecsstat1, nvgpu_readl(g, gr_fecs_ctxsw_mailbox_r(0)),
nvgpu_readl(g, fifo_preempt_r()));
#endif
if (wait_preempt) {
g->ops.fifo.is_preempt_pending(g, preempt_id, preempt_type);
@@ -180,7 +179,7 @@ void gk20a_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
nvgpu_spinlock_acquire(&g->fifo.runlist_submit_lock);
if (count != 0U) {
gk20a_writel(g, fifo_runlist_base_r(),
nvgpu_writel(g, fifo_runlist_base_r(),
fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) |
nvgpu_aperture_mask(g, &runlist->mem[buffer_index],
fifo_runlist_base_target_sys_mem_ncoh_f(),
@@ -188,7 +187,7 @@ void gk20a_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
fifo_runlist_base_target_vid_mem_f()));
}
gk20a_writel(g, fifo_runlist_r(),
nvgpu_writel(g, fifo_runlist_r(),
fifo_runlist_engine_f(runlist_id) |
fifo_eng_runlist_length_f(count));
@@ -205,7 +204,7 @@ int gk20a_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
NVGPU_TIMER_CPU_TIMER);
do {
if ((gk20a_readl(g, fifo_eng_runlist_r(runlist_id)) &
if ((nvgpu_readl(g, fifo_eng_runlist_r(runlist_id)) &
fifo_eng_runlist_pending_true_f()) == 0U) {
ret = 0;
break;
@@ -238,7 +237,7 @@ void gk20a_runlist_write_state(struct gk20a *g, u32 runlists_mask,
i++;
}
reg_val = gk20a_readl(g, fifo_sched_disable_r());
reg_val = nvgpu_readl(g, fifo_sched_disable_r());
if (runlist_state == RUNLIST_DISABLED) {
reg_val |= reg_mask;
@@ -246,7 +245,7 @@ void gk20a_runlist_write_state(struct gk20a *g, u32 runlists_mask,
reg_val &= ~reg_mask;
}
gk20a_writel(g, fifo_sched_disable_r(), reg_val);
nvgpu_writel(g, fifo_sched_disable_r(), reg_val);
}

0
drivers/gpu/nvgpu/common/fifo/runlist_gk20a.h → drivers/gpu/nvgpu/hal/fifo/runlist_gk20a.h
View File

0
drivers/gpu/nvgpu/common/fifo/runlist_gv100.c → drivers/gpu/nvgpu/hal/fifo/runlist_gv100.c
View File

0
drivers/gpu/nvgpu/common/fifo/runlist_gv100.h → drivers/gpu/nvgpu/hal/fifo/runlist_gv100.h
View File

20
drivers/gpu/nvgpu/common/fifo/runlist_gv11b.c → drivers/gpu/nvgpu/hal/fifo/runlist_gv11b.c
View File

@@ -75,39 +75,39 @@ void gv11b_runlist_get_tsg_entry(struct tsg_gk20a *tsg, u32 *runlist)
}
void gv11b_runlist_get_ch_entry(struct channel_gk20a *c, u32 *runlist)
void gv11b_runlist_get_ch_entry(struct channel_gk20a *ch, u32 *runlist)
{
struct gk20a *g = c->g;
struct gk20a *g = ch->g;
u32 addr_lo, addr_hi;
u32 runlist_entry;
/* Time being use 0 pbdma sequencer */
runlist_entry = ram_rl_entry_type_channel_v() |
ram_rl_entry_chan_runqueue_selector_f(
c->runqueue_sel) |
ch->runqueue_sel) |
ram_rl_entry_chan_userd_target_f(
nvgpu_aperture_mask(g, c->userd_mem,
nvgpu_aperture_mask(g, ch->userd_mem,
ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(),
ram_rl_entry_chan_userd_target_sys_mem_coh_v(),
ram_rl_entry_chan_userd_target_vid_mem_v())) |
ram_rl_entry_chan_inst_target_f(
nvgpu_aperture_mask(g, &c->inst_block,
nvgpu_aperture_mask(g, &ch->inst_block,
ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(),
ram_rl_entry_chan_inst_target_sys_mem_coh_v(),
ram_rl_entry_chan_inst_target_vid_mem_v()));
addr_lo = u64_lo32(c->userd_iova) >>
addr_lo = u64_lo32(ch->userd_iova) >>
ram_rl_entry_chan_userd_ptr_align_shift_v();
addr_hi = u64_hi32(c->userd_iova);
addr_hi = u64_hi32(ch->userd_iova);
runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo);
runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi);
addr_lo = u64_lo32(nvgpu_inst_block_addr(g, &c->inst_block)) >>
addr_lo = u64_lo32(nvgpu_inst_block_addr(g, &ch->inst_block)) >>
ram_rl_entry_chan_inst_ptr_align_shift_v();
addr_hi = u64_hi32(nvgpu_inst_block_addr(g, &c->inst_block));
addr_hi = u64_hi32(nvgpu_inst_block_addr(g, &ch->inst_block));
runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) |
ram_rl_entry_chid_f(c->chid);
ram_rl_entry_chid_f(ch->chid);
runlist[3] = ram_rl_entry_chan_inst_ptr_hi_f(addr_hi);
nvgpu_log_info(g, "gv11b channel runlist [0] %x [1] %x [2] %x [3] %x\n",

2
drivers/gpu/nvgpu/common/fifo/runlist_gv11b.h → drivers/gpu/nvgpu/hal/fifo/runlist_gv11b.h
View File

@@ -31,6 +31,6 @@ int gv11b_runlist_reschedule(struct channel_gk20a *ch, bool preempt_next);
u32 gv11b_runlist_count_max(void);
u32 gv11b_runlist_entry_size(struct gk20a *g);
void gv11b_runlist_get_tsg_entry(struct tsg_gk20a *tsg, u32 *runlist);
void gv11b_runlist_get_ch_entry(struct channel_gk20a *c, u32 *runlist);
void gv11b_runlist_get_ch_entry(struct channel_gk20a *ch, u32 *runlist);
#endif /* NVGPU_RUNLIST_GV11B_H */

0
drivers/gpu/nvgpu/common/fifo/runlist_tu104.c → drivers/gpu/nvgpu/hal/fifo/runlist_tu104.c
View File

0
drivers/gpu/nvgpu/common/fifo/runlist_tu104.h → drivers/gpu/nvgpu/hal/fifo/runlist_tu104.h
View File

6
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -69,6 +69,9 @@
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/ramin_gp10b.h"
#include "hal/fifo/ramin_gv11b.h"
#include "hal/fifo/runlist_gk20a.h"
#include "hal/fifo/runlist_gv11b.h"
#include "hal/fifo/runlist_tu104.h"
#include "hal/fifo/tsg_gv11b.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/userd_gv11b.h"
@@ -128,9 +131,6 @@
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_tu104.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/runlist_gv11b.h"
#include "common/fifo/runlist_tu104.h"
#include "common/fifo/channel_gk20a.h"
#include "common/fifo/channel_gm20b.h"
#include "common/fifo/channel_gv11b.h"