nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: fifo: fix MISRA 10.3 violations

Browse Source 
MISRA Rule 10.3 prohibits assigning objects of different essential or
narrower type. This fixes MISRA 10.3 violations in the fifo unit.

JIRA NVGPU-3115

Change-Id: I5a0e1134f731631faa3aa31b5d88781c200306e0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094444
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-04-09 11:30:45 -04:00
committed by mobile promotions
parent 6489b140ae
commit 8e9ec4f1b7
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -726,7 +726,7 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg)
ENGINE_STATUS_CTX_ID_TYPE_TSGID) ||
(!is_tsg && type ==
ENGINE_STATUS_CTX_ID_TYPE_CHID)) {
engines |= BIT(active_engine_id);
engines |= BIT32(active_engine_id);
}
}
}

2
drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c
View File

@@ -59,7 +59,7 @@ int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
pbdma_gp_base_hi_limit2_f(U32(ilog2(gpfifo_entries))));
nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
ch->g->ops.pbdma.get_signature(ch->g));