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gpu: nvgpu: update doxygen for common.fifo
- Add doxygen comments for nvgpu_tsg_open_common(). - Update return and return value description for 1. nvgpu_fifo_init_support() 2. nvgpu_fifo_setup_sw() 3. nvgpu_fifo_setup_sw_common() 4. nvgpu_channel_init_support() 5. gops_fifo.reset_enable_hw() 6. nvgpu_runlist_get_runlists_mask() Jira NVGPU-6222 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Change-Id: I2ef150d41695afca303f1e083f559d31895ba602 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2482062 GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -657,6 +657,11 @@ void nvgpu_channel_commit_va(struct nvgpu_channel *c);
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* This includes mutexes and list nodes initialization.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ENOMEM in case there is not enough memory to allocate channels.
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* @retval -EINVAL for invalid condition variable value.
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* @retval -EBUSY in case reference condition variable pointer isn't NULL.
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* @retval -EFAULT in case any faults occurred while accessing condition
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* variable or attribute.
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*/
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int nvgpu_channel_init_support(struct gk20a *g, u32 chid);
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@@ -671,6 +676,10 @@ int nvgpu_channel_init_support(struct gk20a *g, u32 chid);
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ENOMEM in case there is not enough memory to allocate channels.
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* @retval -EINVAL for invalid condition variable value.
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* @retval -EBUSY in case reference condition variable pointer isn't NULL.
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* @retval -EFAULT in case any faults occurred while accessing condition
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* variable or attribute.
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*/
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int nvgpu_channel_setup_sw(struct gk20a *g);
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@@ -423,7 +423,11 @@ static inline const char *nvgpu_id_type_to_str(unsigned int id_type)
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* care of h/w specific setup related to FIFO module.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval Error returned by setup_sw and setup_hw routines.
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* @retval -ENOMEM in case there is not enough memory available.
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* @retval -EINVAL in case condition variable has invalid value.
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* @retval -EBUSY in case reference condition variable pointer isn't NULL.
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* @retval -EFAULT in case any faults occurred while accessing condition
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* variable or attribute.
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*/
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int nvgpu_fifo_init_support(struct gk20a *g);
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@@ -439,6 +443,11 @@ int nvgpu_fifo_init_support(struct gk20a *g);
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* Mark FIFO s/w ready by setting #nvgpu_fifo.sw_ready to true.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ENOMEM in case there is not enough memory available.
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* @retval -EINVAL in case condition variable has invalid value.
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* @retval -EBUSY in case reference condition variable pointer isn't NULL.
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* @retval -EFAULT in case any faults occurred while accessing condition
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* variable or attribute.
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*/
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int nvgpu_fifo_setup_sw(struct gk20a *g);
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@@ -456,9 +465,14 @@ int nvgpu_fifo_setup_sw(struct gk20a *g);
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* - Do userd.setup_sw.
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* - Init #nvgpu_fifo.remove_support function pointer.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @note In case of failure, cleanup_sw for the blocks that are already
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* initialized is also taken care of by this function.
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ENOMEM in case there is not enough memory available.
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* @retval -EINVAL in case condition variable has invalid value.
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* @retval -EBUSY in case reference condition variable pointer isn't NULL.
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* @retval -EFAULT in case any faults occurred while accessing condition
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* variable or attribute.
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*/
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int nvgpu_fifo_setup_sw_common(struct gk20a *g);
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@@ -344,11 +344,11 @@ void nvgpu_runlist_unlock_runlists(struct gk20a *g, u32 runlists_mask);
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* looks up for the runlist servicing related channel/TSG.
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*
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* @return A bitmask of runlists servicing specified engines/PBDMAs/channel/TSG.
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* @retval If both #id_type and engine/PBDMAs are known, the function returns
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* the set of runlist servicing #id or engine/PBDMA.
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* @retval If both #id_type and engines/PBDMAs are unknown (i.e.
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* #ID_TYPE_UNKNOWN and both #act_eng_bitmask and #pbdma_bitmask are
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* equal to 0), the function returns a bitmask of all active runlists.
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* @retval Runlist_mask of runlist servicing \a id or engine/PBDMA, if both
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* \a id_type and engine/PBDMAs are known.
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* @retval Runlist_mask of all active runlists, if both \a id_type and
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* engines/PBDMAs are unknown (i.e. #ID_TYPE_UNKNOWN and both
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* \a act_eng_bitmask and #pbdma_bitmask are equal to 0).
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*/
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u32 nvgpu_runlist_get_runlists_mask(struct gk20a *g, u32 id,
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unsigned int id_type, u32 act_eng_bitmask, u32 pbdma_bitmask);
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@@ -210,6 +210,19 @@ struct nvgpu_tsg {
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#endif
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};
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/**
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* @brief Initialize given TSG
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*
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* @param g [in] The GPU driver struct.
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* @param pid [in] The PID of the process.
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*
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* - Set s/w context of the given TSG.
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* - Update given TSG struct with init pointers.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -EINVAL if there is no SM.
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* @retval -ENOMEM if not enough memory is available.
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*/
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int nvgpu_tsg_open_common(struct gk20a *g, struct nvgpu_tsg *tsg, pid_t pid);
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/**
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* @brief Open and initialize unused TSG
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