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gpu: nvgpu: enable lazy bootstrap support for NVRISCV pmu

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Lazy bootstrap is a secure iGPU feature where LS falcons(FECS and
GPCCS) are bootstrapped by LSPMU in both cold boot and recovery boot.
As there is no ACR running after boot, we need LSPMU to bootstrap LS
falcons to support recovery.
In absence of LSPMU, ACR will bootstrap LS falcons but recovery is
not supported.
This CL will enable Low secure falcon manager(lsfm) to support
Lazy bootstrap feature. This will allow nvgpu to send cmds
to lspmu to bootstrap LS falcons.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I65d17cf5e07a45c040a9bb75f75cf18eb509cd4f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506162
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Ramesh Mylavarapu
2021-04-26 23:50:40 +05:30
committed by mobile promotions
parent 5dacead521
commit 4d3a935b1a
3 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/common/gr/gr_falcon.c
View File

@@ -573,8 +573,7 @@ static int gr_falcon_sec2_or_ls_pmu_bootstrap(struct gk20a *g,
} else
#endif
#ifdef CONFIG_NVGPU_LS_PMU
if (g->support_ls_pmu &&
!nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
if (g->support_ls_pmu) {
bootstrap_set = true;
nvgpu_log(g, gpu_dbg_gr, "bootstrap by LS PMU");

13
drivers/gpu/nvgpu/common/pmu/lsfm/lsfm.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -41,12 +41,11 @@
static bool is_lsfm_supported(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_lsfm *lsfm)
{
#if defined(CONFIG_NVGPU_NEXT)
if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
return false;
}
#endif
/*
* Low secure falcon manager is a secure iGPU functionality to support
* Lazy bootstrap feature. Enabling lsfm will allow nvgpu to send cmds
* to lspmu to bootstrap LS falcons.
*/
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY) &&
(lsfm != NULL)) {
return true;

4
drivers/gpu/nvgpu/common/pmu/lsfm/lsfm_sw_gv100.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -41,6 +41,7 @@ static int gv100_pmu_lsfm_init_acr_wpr_region(struct gk20a *g,
sizeof(struct nv_pmu_rpc_struct_acr_init_wpr_region));
rpc.wpr_regionId = 0x1U;
rpc.wpr_offset = 0x0U;
nvgpu_pmu_dbg(g, "Post NV_PMU_RPC_ID_ACR_INIT_WPR_REGION");
PMU_RPC_EXECUTE(status, pmu, ACR, INIT_WPR_REGION, &rpc, 0);
if (status != 0) {
nvgpu_err(g, "Failed to execute RPC status=0x%x",
@@ -85,6 +86,7 @@ static int gv100_pmu_lsfm_bootstrap_ls_falcon(struct gk20a *g,
sizeof(struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons));
rpc.falcon_id_mask = falcon_id_mask;
rpc.flags = flags;
nvgpu_pmu_dbg(g, "Post NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS");
PMU_RPC_EXECUTE(status, pmu, ACR, BOOTSTRAP_GR_FALCONS, &rpc, 0);
if (status != 0) {
nvgpu_err(g, "Failed to execute RPC, status=0x%x", status);