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gpu: nvgpu: Deleting falcon's unit gp106 & gv100 support

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-Deleting GP106 & GV100 from falcon unit as GP106 & GV100
 is not supported anymore.

JIRA NVGPU-3243

Change-Id: I931ca7b3cc5d165ff1d2bbfa251079c1d4ecec66
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168083
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-08-05 12:02:45 +05:30
committed by mobile promotions
parent b23dc81f05
commit 4e1d8519c8
9 changed files with 15 additions and 239 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/nvgpu-common.yaml
View File

@@ -285,11 +285,7 @@ falcon:
owner: Sagar K owner: Sagar K
safe: no safe: no
gpu: dgpu gpu: dgpu
sources: [ common/falcon/falcon_sw_gp106.c, sources: [ common/falcon/falcon_sw_tu104.c,
common/falcon/falcon_sw_gv100.c,
common/falcon/falcon_sw_tu104.c,
common/falcon/falcon_sw_gp106.h,
common/falcon/falcon_sw_gv100.h,
common/falcon/falcon_sw_tu104.h ] common/falcon/falcon_sw_tu104.h ]
deps: [ ] deps: [ ]
tags: tags:

2
drivers/gpu/nvgpu/Makefile
View File

@@ -472,8 +472,6 @@ nvgpu-y += \
common/vbios/bios_sw_tu104.o \ common/vbios/bios_sw_tu104.o \
common/falcon/falcon.o \ common/falcon/falcon.o \
common/falcon/falcon_sw_gk20a.o \ common/falcon/falcon_sw_gk20a.o \
common/falcon/falcon_sw_gp106.o \
common/falcon/falcon_sw_gv100.o \
common/falcon/falcon_sw_tu104.o \ common/falcon/falcon_sw_tu104.o \
common/engine_queues/engine_mem_queue.o \ common/engine_queues/engine_mem_queue.o \
common/engine_queues/engine_dmem_queue.o \ common/engine_queues/engine_dmem_queue.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -571,8 +571,6 @@ srcs += common/sec2/sec2.c \
common/vbios/bios.c \ common/vbios/bios.c \
common/vbios/bios_sw_gv100.c \ common/vbios/bios_sw_gv100.c \
common/vbios/bios_sw_tu104.c \ common/vbios/bios_sw_tu104.c \
common/falcon/falcon_sw_gp106.c \
common/falcon/falcon_sw_gv100.c \
common/falcon/falcon_sw_tu104.c \ common/falcon/falcon_sw_tu104.c \
common/acr/acr_sw_tu104.c \ common/acr/acr_sw_tu104.c \
common/mm/allocators/page_allocator.c \ common/mm/allocators/page_allocator.c \

4
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -26,7 +26,6 @@
#include "falcon_sw_gk20a.h" #include "falcon_sw_gk20a.h"
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
#include "falcon_sw_gv100.h"
#include "falcon_sw_tu104.h" #include "falcon_sw_tu104.h"
#endif #endif
@@ -448,9 +447,6 @@ static int falcon_sw_init(struct gk20a *g, struct nvgpu_falcon *flcn)
gk20a_falcon_sw_init(flcn); gk20a_falcon_sw_init(flcn);
break; break;
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
case NVGPU_GPUID_GV100:
gv100_falcon_sw_init(flcn);
break;
case NVGPU_GPUID_TU104: case NVGPU_GPUID_TU104:
tu104_falcon_sw_init(flcn); tu104_falcon_sw_init(flcn);
break; break;

90
drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.c
View File

@@ -1,90 +0,0 @@
/*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/falcon.h>
#include "falcon_sw_gk20a.h"
#include "falcon_sw_gp106.h"
void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
&flcn->flcn_engine_dep_ops;
gk20a_falcon_engine_dependency_ops(flcn);
switch (flcn->flcn_id) {
case FALCON_ID_PMU:
flcn_eng_dep_ops->reset_eng = g->ops.pmu.pmu_reset;
break;
case FALCON_ID_SEC2:
flcn_eng_dep_ops->reset_eng = g->ops.sec2.sec2_reset;
break;
default:
flcn_eng_dep_ops->reset_eng = NULL;
break;
}
}
void gp106_falcon_sw_init(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
switch (flcn->flcn_id) {
case FALCON_ID_PMU:
flcn->flcn_base = g->ops.pmu.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true;
break;
case FALCON_ID_SEC2:
flcn->flcn_base = g->ops.sec2.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;
case FALCON_ID_FECS:
flcn->flcn_base = g->ops.gr.falcon.fecs_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;
case FALCON_ID_GPCCS:
flcn->flcn_base = g->ops.gr.falcon.gpccs_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;
case FALCON_ID_NVDEC:
flcn->flcn_base = g->ops.nvdec.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true;
break;
default:
flcn->is_falcon_supported = false;
break;
}
if (flcn->is_falcon_supported) {
gp106_falcon_engine_dependency_ops(flcn);
} else {
nvgpu_info(g, "falcon 0x%x not supported on %s",
flcn->flcn_id, g->name);
}
}

28
drivers/gpu/nvgpu/common/falcon/falcon_sw_gp106.h
View File

@@ -1,28 +0,0 @@
/*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FALCON_SW_GP106_H
#define NVGPU_FALCON_SW_GP106_H
void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn);
void gp106_falcon_sw_init(struct nvgpu_falcon *flcn);
#endif /* NVGPU_FALCON_SW_GP106_H */

78
drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.c
View File

@@ -1,78 +0,0 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/falcon.h>
#include "falcon_sw_gk20a.h"
#include "falcon_sw_gp106.h"
#include "falcon_sw_gv100.h"
void gv100_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
{
struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
&flcn->flcn_engine_dep_ops;
struct gk20a *g = flcn->g;
gk20a_falcon_engine_dependency_ops(flcn);
switch (flcn->flcn_id) {
case FALCON_ID_GSPLITE:
flcn_eng_dep_ops->reset_eng = g->ops.gsp.gsp_reset;
break;
default:
flcn_eng_dep_ops->reset_eng = NULL;
break;
}
}
void gv100_falcon_sw_init(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
switch (flcn->flcn_id) {
case FALCON_ID_MINION:
flcn->flcn_base = g->ops.nvlink.minion.base_addr(g);
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true;
break;
case FALCON_ID_GSPLITE:
flcn->flcn_base = g->ops.gsp.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;
default:
flcn->is_falcon_supported = false;
break;
}
if (flcn->is_falcon_supported) {
gv100_falcon_engine_dependency_ops(flcn);
} else {
/*
* Forward call to previous chip's SW init
* to fetch info for requested
* falcon as no changes between
* current & previous chips.
*/
gp106_falcon_sw_init(flcn);
}
}

28
drivers/gpu/nvgpu/common/falcon/falcon_sw_gv100.h
View File

@@ -1,28 +0,0 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FALCON_SW_GV100_H
#define NVGPU_FALCON_SW_GV100_H
void gv100_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn);
void gv100_falcon_sw_init(struct nvgpu_falcon *flcn);
#endif /* NVGPU_FALCON_SW_GV100_H */

16
drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c
View File

@@ -23,7 +23,6 @@
#include <nvgpu/falcon.h> #include <nvgpu/falcon.h>
#include "falcon_sw_gk20a.h" #include "falcon_sw_gk20a.h"
#include "falcon_sw_gv100.h"
#include "falcon_sw_tu104.h" #include "falcon_sw_tu104.h"
void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
@@ -35,6 +34,9 @@ void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
gk20a_falcon_engine_dependency_ops(flcn); gk20a_falcon_engine_dependency_ops(flcn);
switch (flcn->flcn_id) { switch (flcn->flcn_id) {
case FALCON_ID_GSPLITE:
flcn_eng_dep_ops->reset_eng = g->ops.gsp.gsp_reset;
break;
case FALCON_ID_SEC2: case FALCON_ID_SEC2:
flcn_eng_dep_ops->reset_eng = g->ops.sec2.sec2_reset; flcn_eng_dep_ops->reset_eng = g->ops.sec2.sec2_reset;
flcn_eng_dep_ops->copy_to_emem = g->ops.sec2.sec2_copy_to_emem; flcn_eng_dep_ops->copy_to_emem = g->ops.sec2.sec2_copy_to_emem;
@@ -52,12 +54,22 @@ void tu104_falcon_sw_init(struct nvgpu_falcon *flcn)
struct gk20a *g = flcn->g; struct gk20a *g = flcn->g;
switch (flcn->flcn_id) { switch (flcn->flcn_id) {
case FALCON_ID_GSPLITE:
flcn->flcn_base = g->ops.gsp.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;
case FALCON_ID_SEC2: case FALCON_ID_SEC2:
flcn->flcn_base = g->ops.sec2.falcon_base_addr(); flcn->flcn_base = g->ops.sec2.falcon_base_addr();
flcn->is_falcon_supported = true; flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true; flcn->is_interrupt_enabled = true;
flcn->emem_supported = true; flcn->emem_supported = true;
break; break;
case FALCON_ID_MINION:
flcn->flcn_base = g->ops.nvlink.minion.base_addr(g);
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true;
break;
case FALCON_ID_NVDEC: case FALCON_ID_NVDEC:
flcn->flcn_base = g->ops.nvdec.falcon_base_addr(); flcn->flcn_base = g->ops.nvdec.falcon_base_addr();
flcn->is_falcon_supported = true; flcn->is_falcon_supported = true;
@@ -81,6 +93,6 @@ void tu104_falcon_sw_init(struct nvgpu_falcon *flcn)
* falcon as no changes between * falcon as no changes between
* current & previous chips. * current & previous chips.
*/ */
gv100_falcon_sw_init(flcn); gk20a_falcon_sw_init(flcn);
} }
} }