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gpu: nvgpu: gv11b: Reorg mc HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I1a5abde46bf079c206dfdf9f8ee35df048565c49 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509603 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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@@ -21,6 +21,7 @@
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#include "gk20a/gk20a.h"
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#include "gk20a/css_gr_gk20a.h"
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#include "gk20a/mc_gk20a.h"
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#include "gk20a/dbg_gpu_gk20a.h"
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#include "gk20a/bus_gk20a.h"
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#include "gk20a/flcn_gk20a.h"
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@@ -29,6 +30,7 @@
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#include "gm20b/gr_gm20b.h"
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#include "gp10b/ltc_gp10b.h"
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#include "gp10b/mc_gp10b.h"
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#include "gp10b/priv_ring_gp10b.h"
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#include "hal_gv11b.h"
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@@ -200,7 +202,23 @@ static const struct gpu_ops gv11b_ops = {
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.pg_gr_load_gating_prod =
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gr_gv11b_pg_gr_load_gating_prod,
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},
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.mc = {
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.intr_enable = mc_gv11b_intr_enable,
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.intr_unit_config = mc_gp10b_intr_unit_config,
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.isr_stall = mc_gp10b_isr_stall,
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.intr_stall = mc_gp10b_intr_stall,
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.intr_stall_pause = mc_gp10b_intr_stall_pause,
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.intr_stall_resume = mc_gp10b_intr_stall_resume,
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.intr_nonstall = mc_gp10b_intr_nonstall,
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.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
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.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
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.enable = gk20a_mc_enable,
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.disable = gk20a_mc_disable,
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.reset = gk20a_mc_reset,
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.boot_0 = gk20a_mc_boot_0,
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.is_intr1_pending = mc_gp10b_is_intr1_pending,
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.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
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},
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.falcon = {
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.falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
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},
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@@ -215,6 +233,7 @@ int gv11b_init_hal(struct gk20a *g)
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gops->ltc = gv11b_ops.ltc;
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gops->clock_gating = gv11b_ops.clock_gating;
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gops->mc = gv11b_ops.mc;
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gops->falcon = gv11b_ops.falcon;
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/* Lone functions */
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@@ -227,7 +246,6 @@ int gv11b_init_hal(struct gk20a *g)
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gops->securegpccs = 0;
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gv11b_init_bus(gops);
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gv11b_init_mc(gops);
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gp10b_init_priv_ring(gops);
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gv11b_init_gr(gops);
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gv11b_init_fecs_trace_ops(gops);
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@@ -24,7 +24,7 @@
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#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
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static void mc_gv11b_intr_enable(struct gk20a *g)
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void mc_gv11b_intr_enable(struct gk20a *g)
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{
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u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
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@@ -57,14 +57,7 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
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}
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static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
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bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
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{
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return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false);
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}
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void gv11b_init_mc(struct gpu_ops *gops)
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{
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gp10b_init_mc(gops);
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gops->mc.intr_enable = mc_gv11b_intr_enable;
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gops->mc.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending;
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}
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -15,5 +15,6 @@
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#define MC_GV11B_H
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struct gk20a;
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void gv11b_init_mc(struct gpu_ops *gops);
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void mc_gv11b_intr_enable(struct gk20a *g);
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bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
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#endif
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