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gpu: nvgpu: pmu use PWRCLK at fixed rate 204MHZ

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- On T234, Getting clock by calling clk.get_rate with CTRL_CLK_DOMAIN_PWRCLK
  domian which eventually pass clk index 1U which access TEGRA234_CLK_GPC0CLK.
- But GPC0 is floor-swept which returns makes clk.get_rate API fail
  (failed to query source clock).

Bug 3998230

Change-Id: I0a674b1856daf2b899827a7aafe0fc4185dd9964
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2862998
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
srajum
2023-02-24 11:47:46 +05:30
committed by mobile promotions
parent ab46ee3335
commit 4ef14a13ff
3 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/pmu/lsfm/lsfm_sw_gm20b.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -169,8 +169,7 @@ int gm20b_pmu_lsfm_pmu_cmd_line_args_copy(struct gk20a *g,
pmu->fw->ops.get_cmd_line_args_size(pmu); pmu->fw->ops.get_cmd_line_args_size(pmu);
/* Copying pmu cmdline args */ /* Copying pmu cmdline args */
pmu->fw->ops.set_cmd_line_args_cpu_freq(pmu, pmu->fw->ops.set_cmd_line_args_cpu_freq(pmu, NVGPU_PWRCLK_RATE);
(u32)g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
pmu->fw->ops.set_cmd_line_args_secure_mode(pmu, 1U); pmu->fw->ops.set_cmd_line_args_secure_mode(pmu, 1U);
pmu->fw->ops.set_cmd_line_args_trace_size( pmu->fw->ops.set_cmd_line_args_trace_size(
pmu, PMU_RTOS_TRACE_BUFSIZE); pmu, PMU_RTOS_TRACE_BUFSIZE);

5
drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -250,8 +250,7 @@ void nvgpu_pmu_rtos_cmdline_args_init(struct gk20a *g, struct nvgpu_pmu *pmu)
pmu->fw->ops.set_cmd_line_args_trace_dma_idx( pmu->fw->ops.set_cmd_line_args_trace_dma_idx(
pmu, GK20A_PMU_DMAIDX_VIRT); pmu, GK20A_PMU_DMAIDX_VIRT);
pmu->fw->ops.set_cmd_line_args_cpu_freq(pmu, pmu->fw->ops.set_cmd_line_args_cpu_freq(pmu, NVGPU_PWRCLK_RATE);
(u32)g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
if (pmu->fw->ops.config_cmd_line_args_super_surface != NULL) { if (pmu->fw->ops.config_cmd_line_args_super_surface != NULL) {
pmu->fw->ops.config_cmd_line_args_super_surface(pmu); pmu->fw->ops.config_cmd_line_args_super_surface(pmu);

2
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -214,6 +214,8 @@ struct nvgpu_clk_pmupstate;
#define PMU_BAR0_READ_FECSERR 9U #define PMU_BAR0_READ_FECSERR 9U
#define PMU_BAR0_WRITE_FECSERR 10U #define PMU_BAR0_WRITE_FECSERR 10U
#define NVGPU_PWRCLK_RATE 204000000UL
#ifdef CONFIG_NVGPU_LS_PMU #ifdef CONFIG_NVGPU_LS_PMU
struct rpc_handler_payload { struct rpc_handler_payload {
void *rpc_buff; void *rpc_buff;