gpu: nvgpu: ACR load split feature support

-Added code to copy SEC2-RTOS ucode to non-wpr blob
  as part of prepare ucode blob.
-Added code to setup & bootstrap GSP, as ACR-ASB needs
 ucode to execute on GSP falcon.
-Defined LSF_FALCON_ID_GSPLITE for GSP falcon
-Defined HSBIN_ACR_AHESASC_DBG/PROD_UCODE &
 HSBIN_ACR_ASB_DBG/PROD_UCODE to hold names
 of ACR AHESASC/ASB ucodes.
-Added defines to hold name of SE2C RTOS ucodes

JIRA NVGPUT-134

Change-Id: I824afed41f785a4ca0fb393bd023db5396c7a399
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790179
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gp106/acr_gp106.c

@@ -67,6 +67,7 @@ static get_ucode_details pmu_acr_supp_ucode_list[] = {
 	pmu_ucode_details,
 	fecs_ucode_details,
 	gpccs_ucode_details,
+	sec2_ucode_details,
 };
 
 void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf)
@@ -388,6 +389,73 @@ rel_sig:
 	return err;
 }
 
+int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
+{
+	struct nvgpu_firmware *sec2_fw, *sec2_desc, *sec2_sig;
+	struct pmu_ucode_desc_v1 *desc;
+	struct lsf_ucode_desc_v1 *lsf_desc;
+	u32 *ucode_image;
+	int err = 0;
+
+	gp106_dbg_pmu(g, "requesting SEC2 ucode in %s", g->name);
+	sec2_fw = nvgpu_request_firmware(g, LSF_SEC2_UCODE_IMAGE_BIN,
+		NVGPU_REQUEST_FIRMWARE_NO_SOC);
+	if (sec2_fw == NULL) {
+		nvgpu_err(g, "failed to load sec2 ucode!!");
+		return -ENOENT;
+	}
+
+	ucode_image = (u32 *)sec2_fw->data;
+
+	gp106_dbg_pmu(g, "requesting SEC2 ucode desc in %s", g->name);
+	sec2_desc = nvgpu_request_firmware(g, LSF_SEC2_UCODE_DESC_BIN,
+		NVGPU_REQUEST_FIRMWARE_NO_SOC);
+	if (sec2_desc == NULL) {
+		nvgpu_err(g, "failed to load SEC2 ucode desc!!");
+		err = -ENOENT;
+		goto release_img_fw;
+	}
+
+	desc = (struct pmu_ucode_desc_v1 *)sec2_desc->data;
+
+	sec2_sig = nvgpu_request_firmware(g, LSF_SEC2_UCODE_SIG_BIN,
+		NVGPU_REQUEST_FIRMWARE_NO_SOC);
+	if (sec2_sig == NULL) {
+		nvgpu_err(g, "failed to load SEC2 sig!!");
+		err = -ENOENT;
+		goto release_desc;
+	}
+
+	lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1));
+	if (lsf_desc == NULL) {
+		err = -ENOMEM;
+		goto release_sig;
+	}
+
+	memcpy(lsf_desc, (void *)sec2_sig->data,
+		min_t(size_t, sizeof(*lsf_desc), sec2_sig->size));
+
+	lsf_desc->falcon_id = LSF_FALCON_ID_SEC2;
+
+	p_img->desc = desc;
+	p_img->data = ucode_image;
+	p_img->data_size = desc->app_start_offset + desc->app_size;
+	p_img->fw_ver = NULL;
+	p_img->header = NULL;
+	p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
+
+	gp106_dbg_pmu(g, "requesting SEC2 ucode in %s done", g->name);
+
+	return err;
+release_sig:
+	nvgpu_release_firmware(g, sec2_sig);
+release_desc:
+	nvgpu_release_firmware(g, sec2_desc);
+release_img_fw:
+	nvgpu_release_firmware(g, sec2_fw);
+	return err;
+}
+
 /*
  * Discover all supported shared data falcon SUB WPRs
  */

drivers/gpu/nvgpu/gp106/acr_gp106.h

@@ -53,6 +53,7 @@ int fecs_ucode_details(struct gk20a *g,
 		struct flcn_ucode_img_v1 *p_img);
 int gpccs_ucode_details(struct gk20a *g,
 		struct flcn_ucode_img_v1 *p_img);
+int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
 int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
 	struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id);
 int lsfm_discover_ucode_images(struct gk20a *g,

drivers/gpu/nvgpu/gv100/gsp_gv100.c

@@ -39,3 +39,75 @@ int gv100_gsp_reset(struct gk20a *g)
 
 	return 0;
 }
+
+static int gsp_flcn_bl_bootstrap(struct gk20a *g,
+	struct nvgpu_falcon_bl_info *bl_info)
+{
+	struct mm_gk20a *mm = &g->mm;
+	u32 data = 0;
+	u32 status = 0;
+
+	gk20a_writel(g, pgsp_falcon_itfen_r(),
+		gk20a_readl(g, pgsp_falcon_itfen_r()) |
+		pgsp_falcon_itfen_ctxen_enable_f());
+
+	gk20a_writel(g, pgsp_falcon_nxtctx_r(),
+		pgsp_falcon_nxtctx_ctxptr_f(
+		nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) |
+		pgsp_falcon_nxtctx_ctxvalid_f(1) |
+		nvgpu_aperture_mask(g, &mm->pmu.inst_block,
+			pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(),
+			pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(),
+			pgsp_falcon_nxtctx_ctxtgt_fb_f()));
+
+	data = gk20a_readl(g, pgsp_falcon_debug1_r());
+	data |= pgsp_falcon_debug1_ctxsw_mode_m();
+	gk20a_writel(g, pgsp_falcon_debug1_r(), data);
+
+	data = gk20a_readl(g, pgsp_falcon_engctl_r());
+	data |= pgsp_falcon_engctl_switch_context_true_f();
+	gk20a_writel(g, pgsp_falcon_engctl_r(), data);
+
+	status = nvgpu_flcn_bl_bootstrap(&g->gsp_flcn, bl_info);
+
+	return status;
+}
+
+int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g,
+	struct hs_acr *acr_desc,
+	struct nvgpu_falcon_bl_info *bl_info)
+{
+	u32 data = 0;
+	int err = 0;
+
+	err = nvgpu_flcn_reset(&g->gsp_flcn);
+	if (err != 0) {
+		goto exit;
+	}
+
+	data = gk20a_readl(g, pgsp_fbif_ctl_r());
+	data |= pgsp_fbif_ctl_allow_phys_no_ctx_allow_f();
+	gk20a_writel(g, pgsp_fbif_ctl_r(), data);
+
+	/* setup apertures - virtual */
+	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+			pgsp_fbif_transcfg_mem_type_physical_f() |
+			pgsp_fbif_transcfg_target_local_fb_f());
+	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+			pgsp_fbif_transcfg_mem_type_virtual_f());
+	/* setup apertures - physical */
+	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+			pgsp_fbif_transcfg_mem_type_physical_f() |
+			pgsp_fbif_transcfg_target_local_fb_f());
+	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+			pgsp_fbif_transcfg_mem_type_physical_f() |
+			pgsp_fbif_transcfg_target_coherent_sysmem_f());
+	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+			pgsp_fbif_transcfg_mem_type_physical_f() |
+			pgsp_fbif_transcfg_target_noncoherent_sysmem_f());
+
+	err = gsp_flcn_bl_bootstrap(g, bl_info);
+
+exit:
+	return err;
+}

drivers/gpu/nvgpu/gv100/gsp_gv100.h

@@ -24,5 +24,8 @@
 #define GSP_GV100_H
 
 int gv100_gsp_reset(struct gk20a *g);
+int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g,
+	struct hs_acr *acr_desc,
+	struct nvgpu_falcon_bl_info *bl_info);
 
 #endif /*GSP_GV100_H */

drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h

@@ -48,7 +48,7 @@
  * Defines a common Light Secure Falcon identifier.
  */
 #define LSF_FALCON_ID_PMU       (0)
-#define LSF_FALCON_ID_RESERVED  (1)
+#define LSF_FALCON_ID_GSPLITE   (1)
 #define LSF_FALCON_ID_FECS      (2)
 #define LSF_FALCON_ID_GPCCS     (3)
 #define LSF_FALCON_ID_SEC2      (7)

drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h

@@ -40,6 +40,14 @@ struct nvgpu_acr;
 
 #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
 #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
+#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
+#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
+#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
+#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin"
+
+#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin"
+#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin"
+#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin"
 
 #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
 

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h

@@ -252,6 +252,26 @@ static inline u32 pgsp_falcon_nxtctx_r(void)
 {
 	return 0x00110054U;
 }
+static inline u32 pgsp_falcon_nxtctx_ctxptr_f(u32 v)
+{
+	return (v & 0xfffffffU) << 0U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_fb_f(void)
+{
+	return 0x0U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(void)
+{
+	return 0x20000000U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(void)
+{
+	return 0x30000000U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxvalid_f(u32 v)
+{
+	return (v & 0x1U) << 30U;
+}
 static inline u32 pgsp_falcon_mailbox0_r(void)
 {
 	return 0x00110040U;
@@ -288,6 +308,14 @@ static inline u32 pgsp_falcon_engctl_r(void)
 {
 	return 0x001100a4U;
 }
+static inline u32 pgsp_falcon_engctl_switch_context_true_f(void)
+{
+	return 0x8U;
+}
+static inline u32 pgsp_falcon_engctl_switch_context_false_f(void)
+{
+	return 0x0U;
+}
 static inline u32 pgsp_falcon_cpuctl_r(void)
 {
 	return 0x00110100U;