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gpu: nvgpu: create class unit

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Created class unit under hal and moved all valid class check related
functionality to this unit. Moved all class defs from gr to a new header
include/nvgpu/class.h.

Moved following hals from gr to newly created class unit:
bool (*is_valid_class)(struct gk20a *g, u32 class_num); -->
		 bool (*is_valid)(u32 class_num);
bool (*is_valid_gfx_class)(struct gk20a *g, u32 class_num); -->
		bool (*is_valid_gfx)(u32 class_num);
bool (*is_valid_compute_class)(struct gk20a *g, u32 class_num); -->
		bool (*is_valid_compute)(u32 class_num);

JIRA NVGPU-3109

Change-Id: I01123e9b984613d4bddb2d8cf23d63410e212408
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095542
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-04-11 12:01:03 -07:00
committed by mobile promotions
parent c4facdc058
commit 4faeea63aa
32 changed files with 565 additions and 300 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -34,6 +34,7 @@
#include "hal/bus/bus_gk20a.h"
#include "hal/bus/bus_gm20b.h"
#include "hal/regops/regops_gp10b.h"
#include "hal/class/class_gp10b.h"
#include "hal/fifo/engines_gm20b.h"
#include "hal/fifo/pbdma_gm20b.h"
#include "hal/fifo/pbdma_gp10b.h"
@@ -128,9 +129,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.handle_sw_method = NULL,
.set_alpha_circular_buffer_size = NULL,
.set_circular_buffer_size = NULL,
.is_valid_class = gr_gp10b_is_valid_class,
.is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
.is_valid_compute_class = gr_gp10b_is_valid_compute_class,
.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
.set_hww_esr_report_mask = NULL,
@@ -362,6 +360,11 @@ static const struct gpu_ops vgpu_gp10b_ops = {
gp10b_gr_init_commit_cbes_reserve,
},
},
.class = {
.is_valid = gp10b_class_is_valid,
.is_valid_gfx = gp10b_class_is_valid_gfx,
.is_valid_compute = gp10b_class_is_valid_compute,
},
.perf = {
.get_pmm_per_chiplet_offset =
gm20b_perf_get_pmm_per_chiplet_offset,
@@ -758,6 +761,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
gops->cbc = vgpu_gp10b_ops.cbc;
gops->ce2 = vgpu_gp10b_ops.ce2;
gops->gr = vgpu_gp10b_ops.gr;
gops->class = vgpu_gp10b_ops.class;
gops->gr.ctxsw_prog = vgpu_gp10b_ops.gr.ctxsw_prog;
gops->gr.config = vgpu_gp10b_ops.gr.config;
gops->fb = vgpu_gp10b_ops.fb;

12
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
View File

@@ -230,7 +230,7 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
return -EINVAL;
}
if (!g->ops.gr.is_valid_class(g, class_num)) {
if (!g->ops.class.is_valid(class_num)) {
nvgpu_err(g, "invalid obj class 0x%x", class_num);
err = -EINVAL;
goto out;
@@ -1248,10 +1248,10 @@ static int vgpu_gr_init_ctxsw_preemption_mode(struct gk20a *g,
if (priv->constants.force_preempt_mode && !graphics_preempt_mode &&
!compute_preempt_mode) {
graphics_preempt_mode = g->ops.gr.is_valid_gfx_class(g, class) ?
graphics_preempt_mode = g->ops.class.is_valid_gfx(class) ?
NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0;
compute_preempt_mode =
g->ops.gr.is_valid_compute_class(g, class) ?
g->ops.class.is_valid_compute(class) ?
NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0;
}
@@ -1280,12 +1280,12 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g,
&msg.params.gr_bind_ctxsw_buffers;
int err = 0;
if (g->ops.gr.is_valid_gfx_class(g, class) &&
if (g->ops.class.is_valid_gfx(class) &&
g->gr.ctx_vars.force_preemption_gfxp) {
graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
}
if (g->ops.gr.is_valid_compute_class(g, class) &&
if (g->ops.class.is_valid_compute(class) &&
g->gr.ctx_vars.force_preemption_cilp) {
compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
}
@@ -1369,7 +1369,7 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g,
break;
}
if (g->ops.gr.is_valid_compute_class(g, class)) {
if (g->ops.class.is_valid_compute(class)) {
switch (compute_preempt_mode) {
case NVGPU_PREEMPTION_MODE_COMPUTE_WFI:
nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx,

10
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -23,6 +23,7 @@
#include "hal/bus/bus_gk20a.h"
#include "hal/bus/bus_gm20b.h"
#include "hal/regops/regops_gv11b.h"
#include "hal/class/class_gv11b.h"
#include "hal/fifo/engines_gv11b.h"
#include "hal/fifo/pbdma_gm20b.h"
#include "hal/fifo/pbdma_gp10b.h"
@@ -151,9 +152,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.handle_sw_method = NULL,
.set_alpha_circular_buffer_size = NULL,
.set_circular_buffer_size = NULL,
.is_valid_class = gr_gv11b_is_valid_class,
.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
.is_valid_compute_class = gr_gv11b_is_valid_compute_class,
.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
.set_hww_esr_report_mask = NULL,
@@ -423,6 +421,11 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.handle_tex_exception = NULL,
},
},
.class = {
.is_valid = gv11b_class_is_valid,
.is_valid_gfx = gv11b_class_is_valid_gfx,
.is_valid_compute = gv11b_class_is_valid_compute,
},
.perf = {
.get_pmm_per_chiplet_offset =
gv11b_perf_get_pmm_per_chiplet_offset,
@@ -845,6 +848,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
gops->cbc = vgpu_gv11b_ops.cbc;
gops->ce2 = vgpu_gv11b_ops.ce2;
gops->gr = vgpu_gv11b_ops.gr;
gops->class = vgpu_gv11b_ops.class;
gops->gr.ctxsw_prog = vgpu_gv11b_ops.gr.ctxsw_prog;
gops->gr.config = vgpu_gv11b_ops.gr.config;
gops->fb = vgpu_gv11b_ops.fb;