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gpu: nvgpu: fecs ctxsw trace for gm20b

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Register gk20a non-arch-specific functions for gm20b
gpu_ops.fecs_trace,

Register nvgpu_os_linux_ops.fecs_trace.init_debugfs

gp10b_fecs_trace_flush is now replaced by gm20b_fecs_trace_flush in
fecs_trace_gm20b.* and the fecs_trace_gp10b.* files are removed.

Bug 2052906

Change-Id: Ie7598dbfe876e68ec0a1e2250dff9fa2de3c975f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088526
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2019-04-03 13:39:19 +05:30
committed by mobile promotions
parent dc82262b99
commit 4ffad99a16
9 changed files with 53 additions and 83 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/Makefile
View File

@@ -170,7 +170,6 @@ nvgpu-y += \
hal/gr/ecc/ecc_gv11b.o \
hal/gr/ecc/ecc_tu104.o \
hal/gr/fecs_trace/fecs_trace_gm20b.o \
hal/gr/fecs_trace/fecs_trace_gp10b.o \
hal/gr/fecs_trace/fecs_trace_gv11b.o \
hal/gr/zcull/zcull_gm20b.o \
hal/gr/zcull/zcull_gv11b.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -283,7 +283,6 @@ srcs += common/sim/sim.c \
hal/gr/ecc/ecc_gv11b.c \
hal/gr/ecc/ecc_tu104.c \
hal/gr/fecs_trace/fecs_trace_gm20b.c \
hal/gr/fecs_trace/fecs_trace_gp10b.c \
hal/gr/fecs_trace/fecs_trace_gv11b.c \
hal/gr/zcull/zcull_gm20b.c \
hal/gr/zcull/zcull_gv11b.c \

16
drivers/gpu/nvgpu/hal/gr/fecs_trace/fecs_trace_gm20b.c
View File

@@ -23,6 +23,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/log.h>
#include <nvgpu/io.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/power_features/pg.h>
#include "fecs_trace_gm20b.h"
@@ -31,6 +32,21 @@
#ifdef CONFIG_GK20A_CTXSW_TRACE
int gm20b_fecs_trace_flush(struct gk20a *g)
{
int err;
nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " ");
err = nvgpu_pg_elpg_protected_call(g,
g->ops.gr.falcon.ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_FECS_TRACE_FLUSH, 0U, NULL));
if (err != 0)
nvgpu_err(g, "write timestamp record failed");
return err;
}
int gm20b_fecs_trace_get_read_index(struct gk20a *g)
{
return nvgpu_pg_elpg_protected_call(g,

1
drivers/gpu/nvgpu/hal/gr/fecs_trace/fecs_trace_gm20b.h
View File

@@ -27,6 +27,7 @@
struct gk20a;
int gm20b_fecs_trace_flush(struct gk20a *g);
int gm20b_fecs_trace_get_read_index(struct gk20a *g);
int gm20b_fecs_trace_get_write_index(struct gk20a *g);
int gm20b_fecs_trace_set_read_index(struct gk20a *g, int index);

48
drivers/gpu/nvgpu/hal/gr/fecs_trace/fecs_trace_gp10b.c
View File

@@ -1,48 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/log.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/power_features/pg.h>
#include "gk20a/gr_gk20a.h"
#include "fecs_trace_gp10b.h"
#ifdef CONFIG_GK20A_CTXSW_TRACE
int gp10b_fecs_trace_flush(struct gk20a *g)
{
int err;
nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " ");
err = nvgpu_pg_elpg_protected_call(g,
g->ops.gr.falcon.ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_FECS_TRACE_FLUSH, 0U, NULL));
if (err != 0)
nvgpu_err(g, "write timestamp record failed");
return err;
}
#endif /* CONFIG_GK20A_CTXSW_TRACE */

30
drivers/gpu/nvgpu/hal/gr/fecs_trace/fecs_trace_gp10b.h
View File

@@ -1,30 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FECS_TRACE_GP10B_H
#define NVGPU_FECS_TRACE_GP10B_H
struct gk20a;
int gp10b_fecs_trace_flush(struct gk20a *g);
#endif /* NVGPU_FECS_TRACE_GP10B_H */

27
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -39,6 +39,7 @@
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/setup.h>
#include <nvgpu/pmu/pmu_perfmon.h>
#include <nvgpu/gr/fecs_trace.h>
#include "hal/mm/cache/flush_gk20a.h"
#include "hal/mc/mc_gm20b.h"
@@ -78,6 +79,7 @@
#include "hal/gr/intr/gr_intr_gm20b.h"
#include "hal/gr/config/gr_config_gm20b.h"
#include "hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
#include "hal/gr/fecs_trace/fecs_trace_gm20b.h"
#include "hal/pmu/pmu_gk20a.h"
#include "hal/pmu/pmu_gm20b.h"
#include "hal/falcon/falcon_gk20a.h"
@@ -375,6 +377,30 @@ static const struct gpu_ops gm20b_ops = {
gm20b_gr_config_get_pd_dist_skip_table_size,
.init_sm_id_table = gm20b_gr_config_init_sm_id_table,
},
#ifdef CONFIG_GK20A_CTXSW_TRACE
.fecs_trace = {
.alloc_user_buffer = nvgpu_gr_fecs_trace_ring_alloc,
.free_user_buffer = nvgpu_gr_fecs_trace_ring_free,
.get_mmap_user_buffer_info =
nvgpu_gr_fecs_trace_get_mmap_buffer_info,
.init = nvgpu_gr_fecs_trace_init,
.deinit = nvgpu_gr_fecs_trace_deinit,
.enable = nvgpu_gr_fecs_trace_enable,
.disable = nvgpu_gr_fecs_trace_disable,
.is_enabled = nvgpu_gr_fecs_trace_is_enabled,
.reset = nvgpu_gr_fecs_trace_reset,
.flush = gm20b_fecs_trace_flush,
.poll = nvgpu_gr_fecs_trace_poll,
.bind_channel = nvgpu_gr_fecs_trace_bind_channel,
.unbind_channel = nvgpu_gr_fecs_trace_unbind_channel,
.max_entries = nvgpu_gr_fecs_trace_max_entries,
.get_buffer_full_mailbox_val =
gm20b_fecs_trace_get_buffer_full_mailbox_val,
.get_read_index = gm20b_fecs_trace_get_read_index,
.get_write_index = gm20b_fecs_trace_get_write_index,
.set_read_index = gm20b_fecs_trace_set_read_index,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.setup = {
.bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull,
.alloc_obj_ctx = nvgpu_gr_setup_alloc_obj_ctx,
@@ -1115,6 +1141,7 @@ int gm20b_init_hal(struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
/* Read fuses to check if gpu needs to boot in secure/non-secure mode */
if (gops->fuse.check_priv_security(g) != 0) {

3
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -86,7 +86,6 @@
#include "hal/rc/rc_gk20a.h"
#include "hal/gr/ecc/ecc_gp10b.h"
#include "hal/gr/fecs_trace/fecs_trace_gm20b.h"
#include "hal/gr/fecs_trace/fecs_trace_gp10b.h"
#include "hal/gr/config/gr_config_gm20b.h"
#include "hal/gr/zbc/zbc_gp10b.h"
#include "hal/gr/zcull/zcull_gm20b.h"
@@ -437,7 +436,7 @@ static const struct gpu_ops gp10b_ops = {
.disable = nvgpu_gr_fecs_trace_disable,
.is_enabled = nvgpu_gr_fecs_trace_is_enabled,
.reset = nvgpu_gr_fecs_trace_reset,
.flush = gp10b_fecs_trace_flush,
.flush = gm20b_fecs_trace_flush,
.poll = nvgpu_gr_fecs_trace_poll,
.bind_channel = nvgpu_gr_fecs_trace_bind_channel,
.unbind_channel = nvgpu_gr_fecs_trace_unbind_channel,

9
drivers/gpu/nvgpu/os/linux/os_ops_gm20b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -18,6 +18,7 @@
#include "cde_gm20b.h"
#include "debug_clk_gm20b.h"
#include "debug_fecs_trace.h"
static struct nvgpu_os_linux_ops gm20b_os_linux_ops = {
#ifdef CONFIG_NVGPU_SUPPORT_CDE
@@ -28,6 +29,10 @@ static struct nvgpu_os_linux_ops gm20b_os_linux_ops = {
.clk = {
.init_debugfs = gm20b_clk_init_debugfs,
},
.fecs_trace = {
.init_debugfs = nvgpu_fecs_trace_init_debugfs,
},
};
void nvgpu_gm20b_init_os_ops(struct nvgpu_os_linux *l)
@@ -36,4 +41,6 @@ void nvgpu_gm20b_init_os_ops(struct nvgpu_os_linux *l)
l->ops.cde = gm20b_os_linux_ops.cde;
#endif
l->ops.clk = gm20b_os_linux_ops.clk;
l->ops.fecs_trace = gm20b_os_linux_ops.fecs_trace;
}