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gpu: nvgpu: Remove setting of PRI timeout

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PRI timeout should always use the HW initialization value. Do not set it
explicitly.

JIRA NVGPU-588

Change-Id: Idb63caba07c5fa7e0439e572861443f2783d0adc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730892
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-05-24 15:25:41 -07:00
committed by Tejal Kudav
parent f9a2f449a5
commit 5215d65c25
5 changed files with 2 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/nvgpu/common/bus/bus_gk20a.c
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@@ -32,29 +32,14 @@
void gk20a_bus_init_hw(struct gk20a *g)
{
u32 timeout_period, intr_en_mask = 0;
if (nvgpu_platform_is_silicon(g))
timeout_period = g->default_pri_timeout ?
g->default_pri_timeout : 0x186A0;
else
timeout_period = 0x186A0;
u32 intr_en_mask = 0;
if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
intr_en_mask = bus_intr_en_0_pri_squash_m() |
bus_intr_en_0_pri_fecserr_m() |
bus_intr_en_0_pri_timeout_m();
gk20a_writel(g,
timer_pri_timeout_r(),
timer_pri_timeout_period_f(timeout_period) |
timer_pri_timeout_en_en_enabled_f());
} else {
gk20a_writel(g,
timer_pri_timeout_r(),
timer_pri_timeout_period_f(timeout_period) |
timer_pri_timeout_en_en_disabled_f());
}
gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask);
}

1
drivers/gpu/nvgpu/common/linux/driver_common.c
View File

@@ -158,7 +158,6 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_GPU_CAN_BLCG,
nvgpu_platform_is_silicon(g) ? platform->can_blcg : false);
g->default_pri_timeout = platform->default_pri_timeout;
g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
g->has_syncpoints = platform->has_syncpoints;

9
drivers/gpu/nvgpu/common/linux/pci.c
View File

@@ -90,7 +90,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = true,
.can_blcg = true,
.can_elcg = true,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,
@@ -127,7 +126,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = true,
.can_blcg = true,
.can_elcg = true,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,
@@ -164,7 +162,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = true,
.can_blcg = true,
.can_elcg = true,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,
@@ -201,7 +198,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = true,
.can_blcg = true,
.can_elcg = true,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,
@@ -238,7 +234,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = false,
.can_blcg = false,
.can_elcg = false,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,
@@ -273,7 +268,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = false,
.can_blcg = false,
.can_elcg = false,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,
@@ -308,7 +302,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = false,
.can_blcg = false,
.can_elcg = false,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,
@@ -344,7 +337,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = true,
.can_blcg = true,
.can_elcg = true,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,
@@ -380,7 +372,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_slcg = false,
.can_blcg = false,
.can_elcg = false,
.default_pri_timeout = 0x3ff,
.disable_aspm = true,

5
drivers/gpu/nvgpu/common/linux/platform_gk20a.h
View File

@@ -120,11 +120,6 @@ struct gk20a_platform {
*/
bool force_reset_in_do_idle;
/* default pri timeout, on PCIe it should be lower than timeout
* detection
*/
u32 default_pri_timeout;
/* guest/vm id, needed for IPA to PA transation */
int vmid;

2
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -1353,8 +1353,6 @@ struct gk20a {
bool forced_reset;
bool allow_all;
u32 default_pri_timeout;
u32 ptimer_src_freq;
bool can_railgate;