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gpu: nvgpu: Remove direct MC and GR deps from bus

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bus_gk20a.c had some debug dump references to MC and GR registers.
The dumps have not been very useful, so instead of refactoring the
code just remove the dumps.

JIRA NVGPU-588

Change-Id: Id974731716d058ef4a3fe77240c11b1c53db169c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730891
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-05-24 13:46:53 -07:00
committed by Tejal Kudav
parent dbb8792baf
commit f9a2f449a5
1 changed files with 0 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/common/bus/bus_gk20a.c
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@@ -28,8 +28,6 @@
#include "bus_gk20a.h"
#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
void gk20a_bus_init_hw(struct gk20a *g)
@@ -70,9 +68,6 @@ void gk20a_bus_isr(struct gk20a *g)
bus_intr_0_pri_fecserr_m() |
bus_intr_0_pri_timeout_m())) {
nvgpu_log(g, gpu_dbg_intr, "pmc_enable : 0x%x",
gk20a_readl(g, mc_enable_r()));
save0 = gk20a_readl(g, timer_pri_timeout_save_0_r());
if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) {
/*
@@ -99,11 +94,6 @@ void gk20a_bus_isr(struct gk20a *g)
if (g->ops.priv_ring.decode_error_code)
g->ops.priv_ring.decode_error_code(g,
fecs_errcode);
if ((fecs_errcode & 0xffffff00) == 0xbadf1300)
nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: "
"0x%08x",
gk20a_readl(g, gr_gpc0_fs_gpc_r()));
}
} else {