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gpu: nvpgu: Remove FECS override sysfs API

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FECS override PMU support was removed with http://git-master/1297370.
Remove the sysfs API that is wired to that.

Change-Id: I5802e5a8dd78b80c3d255dd93587b24df9203fca
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1507934
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-06-23 08:49:42 -07:00
committed by mobile promotions
parent 69222f2de6
commit 52445fba1f
6 changed files with 0 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -750,8 +750,6 @@ struct gpu_ops {
int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock);
u32 (*pmu_pg_param_post_init)(struct gk20a *g);
int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd)
(struct gk20a *g, u32 mask);
void (*dump_secure_fuses)(struct gk20a *g);
int (*reset)(struct gk20a *g);
int (*falcon_wait_for_halt)(struct gk20a *g,

1
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
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@@ -739,7 +739,6 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
gops->pmu.pmu_lpwr_enable_pg = NULL;
gops->pmu.pmu_lpwr_disable_pg = NULL;
gops->pmu.pmu_pg_param_post_init = NULL;
gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
gops->pmu.dump_secure_fuses = NULL;
gops->pmu.is_lazy_bootstrap = NULL;
gops->pmu.is_priv_load = NULL;

1
drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
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@@ -308,7 +308,6 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops)
gops->pmu.pmu_lpwr_enable_pg = NULL;
gops->pmu.pmu_lpwr_disable_pg = NULL;
gops->pmu.pmu_pg_param_post_init = NULL;
gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b;
gops->pmu.reset = NULL;
}

1
drivers/gpu/nvgpu/gp106/pmu_gp106.c
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@@ -438,7 +438,6 @@ void gp106_init_pmu_ops(struct gpu_ops *gops)
gops->pmu.pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg;
gops->pmu.pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg;
gops->pmu.pmu_pg_param_post_init = nvgpu_lpwr_post_init;
gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
gops->pmu.dump_secure_fuses = NULL;
gops->pmu.reset = gp106_falcon_reset;
gops->pmu.mclk_init = gp106_mclk_init;

32
drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c
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@@ -23,36 +23,6 @@
#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH)
static ssize_t ecc_enable_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct gk20a *g = get_gk20a(dev);
u32 ecc_mask;
u32 err = 0;
err = sscanf(buf, "%d", &ecc_mask);
if (err == 1) {
err = g->ops.pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd
(g, ecc_mask);
if (err)
nvgpu_err(g, "ECC override did not happen");
} else
return -EINVAL;
return count;
}
static ssize_t ecc_enable_read(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct gk20a *g = get_gk20a(dev);
return sprintf(buf, "ecc override =0x%x\n",
g->ops.gr.get_lrf_tex_ltc_dram_override(g));
}
static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store);
static ssize_t czf_bypass_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
@@ -87,7 +57,6 @@ void gp10b_create_sysfs(struct device *dev)
g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v();
error |= device_create_file(dev, &dev_attr_ecc_enable);
error |= device_create_file(dev, &dev_attr_czf_bypass);
if (error)
nvgpu_err(g, "Failed to create sysfs attributes!");
@@ -95,6 +64,5 @@ void gp10b_create_sysfs(struct device *dev)
void gp10b_remove_sysfs(struct device *dev)
{
device_remove_file(dev, &dev_attr_ecc_enable);
device_remove_file(dev, &dev_attr_czf_bypass);
}

1
drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
View File

@@ -429,7 +429,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops)
gops->pmu.pmu_lpwr_enable_pg = NULL;
gops->pmu.pmu_lpwr_disable_pg = NULL;
gops->pmu.pmu_pg_param_post_init = NULL;
gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
gops->pmu.reset = NULL;
gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gp10b;
}