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gpu: nvgpu: remove dependency on linux header for regops_gk20a*

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This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.

1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.

JIRA NVGPU-417

Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2017-11-13 13:51:48 +05:30
committed by mobile promotions
parent ba2e59dc41
commit 536ec21b56
12 changed files with 297 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/common/linux/driver_common.c
View File

@@ -31,6 +31,7 @@
#include "os_linux.h"
#include "sysfs.h"
#include "ioctl.h"
#include "gk20a/regops_gk20a.h"
#define EMC3D_DEFAULT_RATIO 750

230
drivers/gpu/nvgpu/common/linux/ioctl_dbg.c
View File

@@ -40,6 +40,8 @@
#include "platform_gk20a.h"
#include "ioctl_dbg.h"
/* turn seriously unwieldy names -> something shorter */
#define REGOP_LINUX(x) NVGPU_DBG_GPU_REG_OP_##x
/* silly allocator - just increment id */
static nvgpu_atomic_t unique_id = NVGPU_ATOMIC_INIT(0);
@@ -596,6 +598,204 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s)
return 0;
}
/*
* Convert common regops op values of the form of NVGPU_DBG_REG_OP_*
* into linux regops op values of the form of NVGPU_DBG_GPU_REG_OP_*
*/
static u32 nvgpu_get_regops_op_values_linux(u32 regops_op)
{
switch (regops_op) {
case REGOP(READ_32):
return REGOP_LINUX(READ_32);
case REGOP(WRITE_32):
return REGOP_LINUX(WRITE_32);
case REGOP(READ_64):
return REGOP_LINUX(READ_64);
case REGOP(WRITE_64):
return REGOP_LINUX(WRITE_64);
case REGOP(READ_08):
return REGOP_LINUX(READ_08);
case REGOP(WRITE_08):
return REGOP_LINUX(WRITE_08);
}
return regops_op;
}
/*
* Convert linux regops op values of the form of NVGPU_DBG_GPU_REG_OP_*
* into common regops op values of the form of NVGPU_DBG_REG_OP_*
*/
static u32 nvgpu_get_regops_op_values_common(u32 regops_op)
{
switch (regops_op) {
case REGOP_LINUX(READ_32):
return REGOP(READ_32);
case REGOP_LINUX(WRITE_32):
return REGOP(WRITE_32);
case REGOP_LINUX(READ_64):
return REGOP(READ_64);
case REGOP_LINUX(WRITE_64):
return REGOP(WRITE_64);
case REGOP_LINUX(READ_08):
return REGOP(READ_08);
case REGOP_LINUX(WRITE_08):
return REGOP(WRITE_08);
}
return regops_op;
}
/*
* Convert common regops type values of the form of NVGPU_DBG_REG_OP_TYPE_*
* into linux regops type values of the form of NVGPU_DBG_GPU_REG_OP_TYPE_*
*/
static u32 nvgpu_get_regops_type_values_linux(u32 regops_type)
{
switch (regops_type) {
case REGOP(TYPE_GLOBAL):
return REGOP_LINUX(TYPE_GLOBAL);
case REGOP(TYPE_GR_CTX):
return REGOP_LINUX(TYPE_GR_CTX);
case REGOP(TYPE_GR_CTX_TPC):
return REGOP_LINUX(TYPE_GR_CTX_TPC);
case REGOP(TYPE_GR_CTX_SM):
return REGOP_LINUX(TYPE_GR_CTX_SM);
case REGOP(TYPE_GR_CTX_CROP):
return REGOP_LINUX(TYPE_GR_CTX_CROP);
case REGOP(TYPE_GR_CTX_ZROP):
return REGOP_LINUX(TYPE_GR_CTX_ZROP);
case REGOP(TYPE_GR_CTX_QUAD):
return REGOP_LINUX(TYPE_GR_CTX_QUAD);
}
return regops_type;
}
/*
* Convert linux regops type values of the form of NVGPU_DBG_GPU_REG_OP_TYPE_*
* into common regops type values of the form of NVGPU_DBG_REG_OP_TYPE_*
*/
static u32 nvgpu_get_regops_type_values_common(u32 regops_type)
{
switch (regops_type) {
case REGOP_LINUX(TYPE_GLOBAL):
return REGOP(TYPE_GLOBAL);
case REGOP_LINUX(TYPE_GR_CTX):
return REGOP(TYPE_GR_CTX);
case REGOP_LINUX(TYPE_GR_CTX_TPC):
return REGOP(TYPE_GR_CTX_TPC);
case REGOP_LINUX(TYPE_GR_CTX_SM):
return REGOP(TYPE_GR_CTX_SM);
case REGOP_LINUX(TYPE_GR_CTX_CROP):
return REGOP(TYPE_GR_CTX_CROP);
case REGOP_LINUX(TYPE_GR_CTX_ZROP):
return REGOP(TYPE_GR_CTX_ZROP);
case REGOP_LINUX(TYPE_GR_CTX_QUAD):
return REGOP(TYPE_GR_CTX_QUAD);
}
return regops_type;
}
/*
* Convert common regops status values of the form of NVGPU_DBG_REG_OP_STATUS_*
* into linux regops type values of the form of NVGPU_DBG_GPU_REG_OP_STATUS_*
*/
static u32 nvgpu_get_regops_status_values_linux(u32 regops_status)
{
switch (regops_status) {
case REGOP(STATUS_SUCCESS):
return REGOP_LINUX(STATUS_SUCCESS);
case REGOP(STATUS_INVALID_OP):
return REGOP_LINUX(STATUS_INVALID_OP);
case REGOP(STATUS_INVALID_TYPE):
return REGOP_LINUX(STATUS_INVALID_TYPE);
case REGOP(STATUS_INVALID_OFFSET):
return REGOP_LINUX(STATUS_INVALID_OFFSET);
case REGOP(STATUS_UNSUPPORTED_OP):
return REGOP_LINUX(STATUS_UNSUPPORTED_OP);
case REGOP(STATUS_INVALID_MASK ):
return REGOP_LINUX(STATUS_INVALID_MASK);
}
return regops_status;
}
/*
* Convert linux regops status values of the form of NVGPU_DBG_GPU_REG_OP_STATUS_*
* into common regops type values of the form of NVGPU_DBG_REG_OP_STATUS_*
*/
static u32 nvgpu_get_regops_status_values_common(u32 regops_status)
{
switch (regops_status) {
case REGOP_LINUX(STATUS_SUCCESS):
return REGOP(STATUS_SUCCESS);
case REGOP_LINUX(STATUS_INVALID_OP):
return REGOP(STATUS_INVALID_OP);
case REGOP_LINUX(STATUS_INVALID_TYPE):
return REGOP(STATUS_INVALID_TYPE);
case REGOP_LINUX(STATUS_INVALID_OFFSET):
return REGOP(STATUS_INVALID_OFFSET);
case REGOP_LINUX(STATUS_UNSUPPORTED_OP):
return REGOP(STATUS_UNSUPPORTED_OP);
case REGOP_LINUX(STATUS_INVALID_MASK ):
return REGOP(STATUS_INVALID_MASK);
}
return regops_status;
}
static int nvgpu_get_regops_data_common(struct nvgpu_dbg_gpu_reg_op *in,
struct nvgpu_dbg_reg_op *out, u32 num_ops)
{
u32 i;
if(in == NULL || out == NULL)
return -ENOMEM;
for (i = 0; i < num_ops; i++) {
out[i].op = nvgpu_get_regops_op_values_common(in[i].op);
out[i].type = nvgpu_get_regops_type_values_common(in[i].type);
out[i].status = nvgpu_get_regops_status_values_common(in[i].status);
out[i].quad = in[i].quad;
out[i].group_mask = in[i].group_mask;
out[i].sub_group_mask = in[i].sub_group_mask;
out[i].offset = in[i].offset;
out[i].value_lo = in[i].value_lo;
out[i].value_hi = in[i].value_hi;
out[i].and_n_mask_lo = in[i].and_n_mask_lo;
out[i].and_n_mask_hi = in[i].and_n_mask_hi;
}
return 0;
}
static int nvgpu_get_regops_data_linux(struct nvgpu_dbg_reg_op *in,
struct nvgpu_dbg_gpu_reg_op *out, u32 num_ops)
{
u32 i;
if(in == NULL || out == NULL)
return -ENOMEM;
for (i = 0; i < num_ops; i++) {
out[i].op = nvgpu_get_regops_op_values_linux(in[i].op);
out[i].type = nvgpu_get_regops_type_values_linux(in[i].type);
out[i].status = nvgpu_get_regops_status_values_linux(in[i].status);
out[i].quad = in[i].quad;
out[i].group_mask = in[i].group_mask;
out[i].sub_group_mask = in[i].sub_group_mask;
out[i].offset = in[i].offset;
out[i].value_lo = in[i].value_lo;
out[i].value_hi = in[i].value_hi;
out[i].and_n_mask_lo = in[i].and_n_mask_lo;
out[i].and_n_mask_hi = in[i].and_n_mask_hi;
}
return 0;
}
static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_exec_reg_ops_args *args)
{
@@ -657,36 +857,56 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
if (!powergate_err) {
u64 ops_offset = 0; /* index offset */
struct nvgpu_dbg_gpu_reg_op *linux_fragment = NULL;
linux_fragment = nvgpu_kzalloc(g, g->dbg_regops_tmp_buf_ops *
sizeof(struct nvgpu_dbg_gpu_reg_op));
if (!linux_fragment)
return -ENOMEM;
while (ops_offset < args->num_ops && !err) {
const u64 num_ops =
min(args->num_ops - ops_offset,
(u64)(g->dbg_regops_tmp_buf_ops));
const u64 fragment_size =
num_ops * sizeof(g->dbg_regops_tmp_buf[0]);
num_ops * sizeof(struct nvgpu_dbg_gpu_reg_op);
void __user *const fragment =
(void __user *)(uintptr_t)
(args->ops +
ops_offset * sizeof(g->dbg_regops_tmp_buf[0]));
ops_offset * sizeof(struct nvgpu_dbg_gpu_reg_op));
gk20a_dbg_fn("Regops fragment: start_op=%llu ops=%llu",
ops_offset, num_ops);
gk20a_dbg_fn("Copying regops from userspace");
if (copy_from_user(g->dbg_regops_tmp_buf,
if (copy_from_user(linux_fragment,
fragment, fragment_size)) {
nvgpu_err(g, "copy_from_user failed!");
err = -EFAULT;
break;
}
err = nvgpu_get_regops_data_common(linux_fragment,
g->dbg_regops_tmp_buf, num_ops);
if (err)
break;
err = g->ops.dbg_session_ops.exec_reg_ops(
dbg_s, g->dbg_regops_tmp_buf, num_ops);
err = nvgpu_get_regops_data_linux(g->dbg_regops_tmp_buf,
linux_fragment, num_ops);
if (err)
break;
gk20a_dbg_fn("Copying result to userspace");
if (copy_to_user(fragment, g->dbg_regops_tmp_buf,
if (copy_to_user(fragment, linux_fragment,
fragment_size)) {
nvgpu_err(g, "copy_to_user failed!");
err = -EFAULT;
@@ -696,6 +916,8 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
ops_offset += num_ops;
}
nvgpu_kfree(g, linux_fragment);
/* enable powergate, if previously disabled */
if (is_pg_disabled) {
powergate_err =

3
drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c
View File

@@ -21,13 +21,14 @@
#include "gk20a/gk20a.h"
#include "gk20a/channel_gk20a.h"
#include "gk20a/dbg_gpu_gk20a.h"
#include "gk20a/regops_gk20a.h"
#include "vgpu.h"
#include "dbg_vgpu.h"
#include <nvgpu/bug.h>
int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_reg_op *ops,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops)
{
struct channel_gk20a *ch;

4
drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h
View File

@@ -18,12 +18,12 @@
#define _DBG_VGPU_H_
struct dbg_session_gk20a;
struct nvgpu_dbg_gpu_reg_op;
struct nvgpu_dbg_reg_op;
struct dbg_profiler_object_data;
struct gk20a;
int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_reg_op *ops,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops);
int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
bool vgpu_check_and_set_global_reservation(

1
drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c
View File

@@ -36,6 +36,7 @@
#include "clk_vgpu.h"
#include "gk20a/tsg_gk20a.h"
#include "gk20a/channel_gk20a.h"
#include "gk20a/regops_gk20a.h"
#include "gm20b/hal_gm20b.h"
#include "common/linux/module.h"

4
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -949,7 +949,7 @@ struct gpu_ops {
} debug;
struct {
int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_reg_op *ops,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops);
int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s,
bool disable_powergate);
@@ -1206,7 +1206,7 @@ struct gk20a {
int dbg_timeout_disabled_refcount; /*refcount for timeout disable */
/* must have dbg_sessions_lock before use */
struct nvgpu_dbg_gpu_reg_op *dbg_regops_tmp_buf;
struct nvgpu_dbg_reg_op *dbg_regops_tmp_buf;
u32 dbg_regops_tmp_buf_ops;
/* For perfbuf mapping */

8
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -7749,7 +7749,7 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch)
}
int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
bool ch_is_curr_ctx)
{
@@ -7990,7 +7990,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
}
int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops)
{
struct gk20a *g = ch->g;
@@ -8279,7 +8279,7 @@ void gk20a_gr_resume_all_sms(struct gk20a *g)
int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
struct channel_gk20a *ch, u64 sms, bool enable)
{
struct nvgpu_dbg_gpu_reg_op *ops;
struct nvgpu_dbg_reg_op *ops;
unsigned int i = 0, sm_id;
int err;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -8453,7 +8453,7 @@ int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch)
{
int err = 0;
u32 cache_ctrl, regval;
struct nvgpu_dbg_gpu_reg_op ops;
struct nvgpu_dbg_reg_op ops;
ops.op = REGOP(READ_32);
ops.type = REGOP(TYPE_GR_CTX);

6
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -604,12 +604,12 @@ u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
int gk20a_gr_suspend(struct gk20a *g);
struct nvgpu_dbg_gpu_reg_op;
struct nvgpu_dbg_reg_op;
int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops);
int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
bool ch_is_curr_ctx);
int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,

15
drivers/gpu/nvgpu/gk20a/regops_gk20a.c
View File

@@ -22,9 +22,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <linux/err.h>
#include <uapi/linux/nvgpu.h>
#include "gk20a.h"
#include "gr_gk20a.h"
#include "dbg_gpu_gk20a.h"
@@ -377,12 +374,12 @@ static const u32 gk20a_qctl_whitelist_ranges_count =
static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
u32 *ctx_rd_count, u32 *ctx_wr_count,
struct nvgpu_dbg_gpu_reg_op *ops,
struct nvgpu_dbg_reg_op *ops,
u32 op_count);
int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_reg_op *ops,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops)
{
int err = 0;
@@ -519,7 +516,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_reg_op *op)
struct nvgpu_dbg_reg_op *op)
{
int err = 0;
@@ -559,7 +556,7 @@ static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s,
}
static bool check_whitelists(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_reg_op *op, u32 offset)
struct nvgpu_dbg_reg_op *op, u32 offset)
{
struct gk20a *g = dbg_s->g;
bool valid = false;
@@ -630,7 +627,7 @@ static bool check_whitelists(struct dbg_session_gk20a *dbg_s,
/* note: the op here has already been through validate_reg_op_info */
static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_reg_op *op)
struct nvgpu_dbg_reg_op *op)
{
int err;
u32 buf_offset_lo, buf_offset_addr, num_offsets, offset;
@@ -689,7 +686,7 @@ static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s,
static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
u32 *ctx_rd_count, u32 *ctx_wr_count,
struct nvgpu_dbg_gpu_reg_op *ops,
struct nvgpu_dbg_reg_op *ops,
u32 op_count)
{
u32 i;

50
drivers/gpu/nvgpu/gk20a/regops_gk20a.h
View File

@@ -24,17 +24,63 @@
#ifndef REGOPS_GK20A_H
#define REGOPS_GK20A_H
/*
* Register operations
* All operations are targeted towards first channel
* attached to debug session
*/
/* valid op values */
#define NVGPU_DBG_REG_OP_READ_32 (0x00000000)
#define NVGPU_DBG_REG_OP_WRITE_32 (0x00000001)
#define NVGPU_DBG_REG_OP_READ_64 (0x00000002)
#define NVGPU_DBG_REG_OP_WRITE_64 (0x00000003)
/* note: 8b ops are unsupported */
#define NVGPU_DBG_REG_OP_READ_08 (0x00000004)
#define NVGPU_DBG_REG_OP_WRITE_08 (0x00000005)
/* valid type values */
#define NVGPU_DBG_REG_OP_TYPE_GLOBAL (0x00000000)
#define NVGPU_DBG_REG_OP_TYPE_GR_CTX (0x00000001)
#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_TPC (0x00000002)
#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_SM (0x00000004)
#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_CROP (0x00000008)
#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_ZROP (0x00000010)
/*#define NVGPU_DBG_REG_OP_TYPE_FB (0x00000020)*/
#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_QUAD (0x00000040)
/* valid status values */
#define NVGPU_DBG_REG_OP_STATUS_SUCCESS (0x00000000)
#define NVGPU_DBG_REG_OP_STATUS_INVALID_OP (0x00000001)
#define NVGPU_DBG_REG_OP_STATUS_INVALID_TYPE (0x00000002)
#define NVGPU_DBG_REG_OP_STATUS_INVALID_OFFSET (0x00000004)
#define NVGPU_DBG_REG_OP_STATUS_UNSUPPORTED_OP (0x00000008)
#define NVGPU_DBG_REG_OP_STATUS_INVALID_MASK (0x00000010)
struct nvgpu_dbg_reg_op {
__u8 op;
__u8 type;
__u8 status;
__u8 quad;
__u32 group_mask;
__u32 sub_group_mask;
__u32 offset;
__u32 value_lo;
__u32 value_hi;
__u32 and_n_mask_lo;
__u32 and_n_mask_hi;
};
struct regop_offset_range {
u32 base:24;
u32 count:8;
};
int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_reg_op *ops,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops);
/* turn seriously unwieldy names -> something shorter */
#define REGOP(x) NVGPU_DBG_GPU_REG_OP_##x
#define REGOP(x) NVGPU_DBG_REG_OP_##x
bool reg_op_is_gr_ctx(u8 type);
bool reg_op_is_read(u8 op);

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -2327,7 +2327,7 @@ void gr_gp10b_init_czf_bypass(struct gk20a *g)
int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch)
{
struct nvgpu_dbg_gpu_reg_op ops;
struct nvgpu_dbg_reg_op ops;
ops.op = REGOP(WRITE_32);
ops.type = REGOP(TYPE_GR_CTX);

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -2584,7 +2584,7 @@ fail:
int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
struct channel_gk20a *ch, u64 sms, bool enable)
{
struct nvgpu_dbg_gpu_reg_op *ops;
struct nvgpu_dbg_reg_op *ops;
unsigned int i = 0, sm_id;
int err;