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gpu: nvgpu: Seperate clk monitor from clk unit

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Clock monitor is for monitoring clk status.
This is separated from clk unit which manages the clk.

NVGPU-4491

Change-Id: If83434db7970f1b024f545672a6f1e92ee66dbbc
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313201
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Abdul Salam
2020-03-17 18:12:10 +05:30
committed by Alex Waterman
parent 5ce7d5acff
commit 53bd199e30
8 changed files with 282 additions and 213 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/nvgpu-hal-new.yaml
View File

@@ -140,6 +140,13 @@ clk:
sources: [ hal/clk/clk_tu104.c,
hal/clk/clk_tu104.h ]
clk_mon:
safe: yes
owner: Ramesh M
gpu: dgpu
sources: [ hal/clk/clk_mon_tu104.c,
hal/clk/clk_mon_tu104.h ]
clk_igpu:
safe: no
owner: Ramesh M

1
drivers/gpu/nvgpu/Makefile
View File

@@ -101,6 +101,7 @@ nvgpu-$(CONFIG_NVGPU_DGPU) += \
hal/bus/bus_tu104.o \
hal/class/class_tu104.o \
hal/clk/clk_tu104.o \
hal/clk/clk_mon_tu104.o \
hal/gr/init/gr_init_gv100.o \
hal/gr/init/gr_init_tu104.o \
hal/gr/intr/gr_intr_tu104.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -595,6 +595,7 @@ srcs += common/sec2/sec2.c \
hal/ce/ce_tu104.c \
hal/class/class_tu104.c \
hal/clk/clk_tu104.c \
hal/clk/clk_mon_tu104.c \
hal/gr/init/gr_init_gv100.c \
hal/gr/init/gr_init_tu104.c \
hal/gr/intr/gr_intr_tu104.c \

230
drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c Normal file
View File

@@ -0,0 +1,230 @@
/*
* TU104 Clocks Monitor
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/kmem.h>
#include <nvgpu/io.h>
#include <nvgpu/list.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/soc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/hw/tu104/hw_trim_tu104.h>
#include "clk_mon_tu104.h"
/**
* Mapping between the clk domain and the various clock monitor registers
* The rows represent clock domains starting from index 0 and column represent
* the various registers each domain has, non available domains are set to 0
* for easy accessing, refer nvgpu_pmu_clk_mon_init_domains() for valid domains.
*/
static u32 clock_mon_map_tu104[CLK_CLOCK_MON_DOMAIN_COUNT]
[CLK_CLOCK_MON_REG_TYPE_COUNT] = {
{
trim_gpcclk_fault_threshold_high_r(),
trim_gpcclk_fault_threshold_low_r(),
trim_gpcclk_fault_status_r(),
trim_gpcclk_fault_priv_level_mask_r(),
},
{
trim_xbarclk_fault_threshold_high_r(),
trim_xbarclk_fault_threshold_low_r(),
trim_xbarclk_fault_status_r(),
trim_xbarclk_fault_priv_level_mask_r(),
},
{
trim_sysclk_fault_threshold_high_r(),
trim_sysclk_fault_threshold_low_r(),
trim_sysclk_fault_status_r(),
trim_sysclk_fault_priv_level_mask_r(),
},
{
trim_hubclk_fault_threshold_high_r(),
trim_hubclk_fault_threshold_low_r(),
trim_hubclk_fault_status_r(),
trim_hubclk_fault_priv_level_mask_r(),
},
{
trim_dramclk_fault_threshold_high_r(),
trim_dramclk_fault_threshold_low_r(),
trim_dramclk_fault_status_r(),
trim_dramclk_fault_priv_level_mask_r(),
},
{
trim_hostclk_fault_threshold_high_r(),
trim_hostclk_fault_threshold_low_r(),
trim_hostclk_fault_status_r(),
trim_hostclk_fault_priv_level_mask_r(),
},
{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0},
{
trim_utilsclk_fault_threshold_high_r(),
trim_utilsclk_fault_threshold_low_r(),
trim_utilsclk_fault_status_r(),
trim_utilsclk_fault_priv_level_mask_r(),
},
{
trim_pwrclk_fault_threshold_high_r(),
trim_pwrclk_fault_threshold_low_r(),
trim_pwrclk_fault_status_r(),
trim_pwrclk_fault_priv_level_mask_r(),
},
{
trim_nvdclk_fault_threshold_high_r(),
trim_nvdclk_fault_threshold_low_r(),
trim_nvdclk_fault_status_r(),
trim_nvdclk_fault_priv_level_mask_r(),
},
{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0},
{
trim_xclk_fault_threshold_high_r(),
trim_xclk_fault_threshold_low_r(),
trim_xclk_fault_status_r(),
trim_xclk_fault_priv_level_mask_r(),
},
{
trim_nvl_commonclk_fault_threshold_high_r(),
trim_nvl_commonclk_fault_threshold_low_r(),
trim_nvl_commonclk_fault_status_r(),
trim_nvl_commonclk_fault_priv_level_mask_r(),
},
{
trim_pex_refclk_fault_threshold_high_r(),
trim_pex_refclk_fault_threshold_low_r(),
trim_pex_refclk_fault_status_r(),
trim_pex_refclk_fault_priv_level_mask_r(),
},
{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}
};
static u32 nvgpu_check_for_dc_fault(u32 data)
{
return (trim_fault_status_dc_v(data) ==
trim_fault_status_dc_true_v()) ?
trim_fault_status_dc_m() : 0U;
}
static u32 nvgpu_check_for_lower_threshold_fault(u32 data)
{
return (trim_fault_status_lower_threshold_v(data) ==
trim_fault_status_lower_threshold_true_v()) ?
trim_fault_status_lower_threshold_m() : 0U;
}
static u32 nvgpu_check_for_higher_threshold_fault(u32 data)
{
return (trim_fault_status_higher_threshold_v(data) ==
trim_fault_status_higher_threshold_true_v()) ?
trim_fault_status_higher_threshold_m() : 0U;
}
static u32 nvgpu_check_for_overflow_err(u32 data)
{
return (trim_fault_status_overflow_v(data) ==
trim_fault_status_overflow_true_v()) ?
trim_fault_status_overflow_m() : 0U;
}
static int nvgpu_clk_mon_get_fault(struct gk20a *g, u32 i, u32 data,
struct clk_domains_mon_status_params *clk_mon_status)
{
u32 reg_address;
int status = 0;
/* Fields for faults are same for all clock domains */
clk_mon_status->clk_mon_list[i].clk_domain_fault_status =
((nvgpu_check_for_dc_fault(data)) |
(nvgpu_check_for_lower_threshold_fault(data)) |
(nvgpu_check_for_higher_threshold_fault(data)) |
(nvgpu_check_for_overflow_err(data)));
nvgpu_err(g, "FMON faulted domain 0x%x value 0x%x",
clk_mon_status->clk_mon_list[i].clk_api_domain,
clk_mon_status->clk_mon_list[i].
clk_domain_fault_status);
/* Get the low threshold limit */
reg_address = clock_mon_map_tu104[i][FMON_THRESHOLD_LOW];
data = nvgpu_readl(g, reg_address);
clk_mon_status->clk_mon_list[i].low_threshold =
trim_fault_threshold_low_count_v(data);
/* Get the high threshold limit */
reg_address = clock_mon_map_tu104[i][FMON_THRESHOLD_HIGH];
data = nvgpu_readl(g, reg_address);
clk_mon_status->clk_mon_list[i].high_threshold =
trim_fault_threshold_high_count_v(data);
return status;
}
bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g)
{
u32 fmon_master_status = nvgpu_readl(g, trim_fmon_master_status_r());
if (trim_fmon_master_status_fault_out_v(fmon_master_status) ==
trim_fmon_master_status_fault_out_true_v()) {
return true;
}
return false;
}
int nvgpu_clk_mon_check_status(struct gk20a *g,
struct clk_domains_mon_status_params *clk_mon_status,
u32 domain_mask)
{
u32 reg_address, bit_pos;
u32 data;
int status;
clk_mon_status->clk_mon_domain_mask = domain_mask;
/*
* Parse through each domain and check for faults, each bit set
* represents a domain here
*/
for (bit_pos = 0U; bit_pos < (sizeof(domain_mask) * BITS_PER_BYTE);
bit_pos++) {
if (nvgpu_test_bit(bit_pos, (void *)&domain_mask)) {
clk_mon_status->clk_mon_list[bit_pos].clk_api_domain =
BIT(bit_pos);
reg_address = clock_mon_map_tu104[bit_pos]
[FMON_FAULT_STATUS];
data = nvgpu_readl(g, reg_address);
clk_mon_status->clk_mon_list[bit_pos].
clk_domain_fault_status = 0U;
/* Check FMON fault status, field is same for all */
if (trim_fault_status_fault_out_v(data) ==
trim_fault_status_fault_out_true_v()) {
status = nvgpu_clk_mon_get_fault(g, bit_pos,
data, clk_mon_status);
if (status != 0) {
nvgpu_err(g, "Failed to get status");
return -EINVAL;
}
}
}
}
return 0;
}

40
drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef CLK_MON_TU104_H
#define CLK_MON_TU104_H
/**
* FMON register types
*/
#define FMON_THRESHOLD_HIGH 0x0U
#define FMON_THRESHOLD_LOW 0x1U
#define FMON_FAULT_STATUS 0x2U
#define FMON_FAULT_STATUS_PRIV_MASK 0x3U
#define CLK_CLOCK_MON_REG_TYPE_COUNT 0x4U
#define CLK_MON_BITS_PER_BYTE 0x8U
bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g);
int nvgpu_clk_mon_check_status(struct gk20a *g, struct
clk_domains_mon_status_params *clk_mon_status,
u32 domain_mask);
#endif /* CLK_MON_TU104_H */

198
drivers/gpu/nvgpu/hal/clk/clk_tu104.c
View File

@@ -58,204 +58,6 @@
#define XTAL4X_KHZ 108000
#define BOOT_GPCCLK_MHZ 645U
/**
* Mapping between the clk domain and the various clock monitor registers
* The rows represent clock domains starting from index 0 and column represent
* the various registers each domain has, non available domains are set to 0
* for easy accessing, refer nvgpu_pmu_clk_mon_init_domains() for valid domains.
*/
static u32 clock_mon_map_tu104[CLK_CLOCK_MON_DOMAIN_COUNT]
[CLK_CLOCK_MON_REG_TYPE_COUNT] = {
{
trim_gpcclk_fault_threshold_high_r(),
trim_gpcclk_fault_threshold_low_r(),
trim_gpcclk_fault_status_r(),
trim_gpcclk_fault_priv_level_mask_r(),
},
{
trim_xbarclk_fault_threshold_high_r(),
trim_xbarclk_fault_threshold_low_r(),
trim_xbarclk_fault_status_r(),
trim_xbarclk_fault_priv_level_mask_r(),
},
{
trim_sysclk_fault_threshold_high_r(),
trim_sysclk_fault_threshold_low_r(),
trim_sysclk_fault_status_r(),
trim_sysclk_fault_priv_level_mask_r(),
},
{
trim_hubclk_fault_threshold_high_r(),
trim_hubclk_fault_threshold_low_r(),
trim_hubclk_fault_status_r(),
trim_hubclk_fault_priv_level_mask_r(),
},
{
trim_dramclk_fault_threshold_high_r(),
trim_dramclk_fault_threshold_low_r(),
trim_dramclk_fault_status_r(),
trim_dramclk_fault_priv_level_mask_r(),
},
{
trim_hostclk_fault_threshold_high_r(),
trim_hostclk_fault_threshold_low_r(),
trim_hostclk_fault_status_r(),
trim_hostclk_fault_priv_level_mask_r(),
},
{0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0},
{0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0},
{0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0},
{
trim_utilsclk_fault_threshold_high_r(),
trim_utilsclk_fault_threshold_low_r(),
trim_utilsclk_fault_status_r(),
trim_utilsclk_fault_priv_level_mask_r(),
},
{
trim_pwrclk_fault_threshold_high_r(),
trim_pwrclk_fault_threshold_low_r(),
trim_pwrclk_fault_status_r(),
trim_pwrclk_fault_priv_level_mask_r(),
},
{
trim_nvdclk_fault_threshold_high_r(),
trim_nvdclk_fault_threshold_low_r(),
trim_nvdclk_fault_status_r(),
trim_nvdclk_fault_priv_level_mask_r(),
},
{0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0},
{
trim_xclk_fault_threshold_high_r(),
trim_xclk_fault_threshold_low_r(),
trim_xclk_fault_status_r(),
trim_xclk_fault_priv_level_mask_r(),
},
{
trim_nvl_commonclk_fault_threshold_high_r(),
trim_nvl_commonclk_fault_threshold_low_r(),
trim_nvl_commonclk_fault_status_r(),
trim_nvl_commonclk_fault_priv_level_mask_r(),
},
{
trim_pex_refclk_fault_threshold_high_r(),
trim_pex_refclk_fault_threshold_low_r(),
trim_pex_refclk_fault_status_r(),
trim_pex_refclk_fault_priv_level_mask_r(),
},
{0,0,0,0}, {0,0,0,0}, {0,0,0,0}
};
static u32 nvgpu_check_for_dc_fault(u32 data)
{
return (trim_fault_status_dc_v(data) ==
trim_fault_status_dc_true_v()) ?
trim_fault_status_dc_m() : 0U;
}
static u32 nvgpu_check_for_lower_threshold_fault(u32 data)
{
return (trim_fault_status_lower_threshold_v(data) ==
trim_fault_status_lower_threshold_true_v()) ?
trim_fault_status_lower_threshold_m() : 0U;
}
static u32 nvgpu_check_for_higher_threshold_fault(u32 data)
{
return (trim_fault_status_higher_threshold_v(data) ==
trim_fault_status_higher_threshold_true_v()) ?
trim_fault_status_higher_threshold_m() : 0U;
}
static u32 nvgpu_check_for_overflow_err(u32 data)
{
return (trim_fault_status_overflow_v(data) ==
trim_fault_status_overflow_true_v()) ?
trim_fault_status_overflow_m() : 0U;
}
static int nvgpu_clk_mon_get_fault(struct gk20a *g, u32 i, u32 data,
struct clk_domains_mon_status_params *clk_mon_status)
{
u32 reg_address;
int status = 0;
/* Fields for faults are same for all clock domains */
clk_mon_status->clk_mon_list[i].clk_domain_fault_status =
((nvgpu_check_for_dc_fault(data)) |
(nvgpu_check_for_lower_threshold_fault(data)) |
(nvgpu_check_for_higher_threshold_fault(data)) |
(nvgpu_check_for_overflow_err(data)));
nvgpu_err(g, "FMON faulted domain 0x%x value 0x%x",
clk_mon_status->clk_mon_list[i].clk_api_domain,
clk_mon_status->clk_mon_list[i].
clk_domain_fault_status);
/* Get the low threshold limit */
reg_address = clock_mon_map_tu104[i][FMON_THRESHOLD_LOW];
data = nvgpu_readl(g, reg_address);
clk_mon_status->clk_mon_list[i].low_threshold =
trim_fault_threshold_low_count_v(data);
/* Get the high threshold limit */
reg_address = clock_mon_map_tu104[i][FMON_THRESHOLD_HIGH];
data = nvgpu_readl(g, reg_address);
clk_mon_status->clk_mon_list[i].high_threshold =
trim_fault_threshold_high_count_v(data);
return status;
}
bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g)
{
u32 fmon_master_status = nvgpu_readl(g, trim_fmon_master_status_r());
if (trim_fmon_master_status_fault_out_v(fmon_master_status) ==
trim_fmon_master_status_fault_out_true_v()) {
return true;
}
return false;
}
int nvgpu_clk_mon_check_status(struct gk20a *g,
struct clk_domains_mon_status_params *clk_mon_status,
u32 domain_mask)
{
u32 reg_address, bit_pos;
u32 data;
int status;
clk_mon_status->clk_mon_domain_mask = domain_mask;
/*
* Parse through each domain and check for faults, each bit set
* represents a domain here
*/
for (bit_pos = 0U; bit_pos < (sizeof(domain_mask) * BITS_PER_BYTE);
bit_pos++) {
if (nvgpu_test_bit(bit_pos, (void *)&domain_mask)) {
clk_mon_status->clk_mon_list[bit_pos].clk_api_domain =
BIT(bit_pos);
reg_address = clock_mon_map_tu104[bit_pos]
[FMON_FAULT_STATUS];
data = nvgpu_readl(g, reg_address);
clk_mon_status->clk_mon_list[bit_pos].
clk_domain_fault_status = 0U;
/* Check FMON fault status, field is same for all */
if (trim_fault_status_fault_out_v(data) ==
trim_fault_status_fault_out_true_v()) {
status = nvgpu_clk_mon_get_fault(g, bit_pos,
data, clk_mon_status);
if (status != 0) {
nvgpu_err(g, "Failed to get status");
return -EINVAL;
}
}
}
}
return 0;
}
#ifdef CONFIG_NVGPU_CLK_ARB
u32 tu104_crystal_clk_hz(struct gk20a *g)
{

17
drivers/gpu/nvgpu/hal/clk/clk_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,16 +25,6 @@
#include <nvgpu/lock.h>
#include <nvgpu/gk20a.h>
/**
* FMON register types
*/
#define FMON_THRESHOLD_HIGH 0x0U
#define FMON_THRESHOLD_LOW 0x1U
#define FMON_FAULT_STATUS 0x2U
#define FMON_FAULT_STATUS_PRIV_MASK 0x3U
#define CLK_CLOCK_MON_REG_TYPE_COUNT 0x4U
#define CLK_MON_BITS_PER_BYTE 0x8U
u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
int tu104_init_clk_support(struct gk20a *g);
u32 tu104_crystal_clk_hz(struct gk20a *g);
@@ -48,8 +38,5 @@ int tu104_clk_domain_get_f_points(
unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain);
void tu104_get_change_seq_time(struct gk20a *g, s64 *change_time);
void tu104_change_host_clk_source(struct gk20a *g);
bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g);
int nvgpu_clk_mon_check_status(struct gk20a *g, struct
clk_domains_mon_status_params *clk_mon_status,
u32 domain_mask);
#endif /* CLK_TU104_H */

1
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -182,6 +182,7 @@
#include "common/clk_arb/clk_arb_gv100.h"
#include "hal/clk/clk_tu104.h"
#include "hal/clk/clk_mon_tu104.h"
#include "hal/fbpa/fbpa_tu104.h"
#include "hal_tu104.h"
#include "hal_tu104_litter.h"