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gpu: nvgpu: per-chip GPCCS exception support

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Adding support for ISR handling of GPCCS exceptions

JIRA: GPUT19X-83

Change-Id: Ia5550aac8f368d8915f6c94aa22478cacbb2bddc
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1480992
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
David Nieto
2017-05-12 11:01:10 -07:00
committed by mobile promotions
parent 7d6d8a7ec3
commit 5570194dc4
2 changed files with 13 additions and 1 deletions
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4
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -309,6 +309,8 @@ struct gpu_ops {
u32 *hww_global_esr);
int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event);
int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc,
u32 gpc_exception);
void (*enable_gpc_exceptions)(struct gk20a *g);
void (*create_gr_sysfs)(struct device *dev);
u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
@@ -749,6 +751,8 @@ struct gpu_ops {
u32 lspmuwprinitdone;
u32 lsfloadedfalconid;
bool fecsbootstrapdone;
void (*handle_ext_irq)(struct gk20a *g, u32 intr);
void (*set_irqmask)(struct gk20a *g);
} pmu;
struct {
void (*disable_slowboot)(struct gk20a *g);

10
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -6350,13 +6350,21 @@ static int gk20a_gr_handle_gpc_exception(struct gk20a *g, bool *post_event,
}
/* Handle GCC exception */
if(gr_gpc0_gpccs_gpc_exception_gcc_v(gpc_exception) &&
if (gr_gpc0_gpccs_gpc_exception_gcc_v(gpc_exception) &&
g->ops.gr.handle_gcc_exception) {
int gcc_ret = 0;
gcc_ret = g->ops.gr.handle_gcc_exception(g, gpc, tpc,
post_event, fault_ch, hww_global_esr);
ret = ret ? ret : gcc_ret;
}
/* Handle GPCCS exceptions */
if (g->ops.gr.handle_gpc_gpccs_exception) {
int ret_ecc = 0;
ret_ecc = g->ops.gr.handle_gpc_gpccs_exception(g, gpc,
gpc_exception);
ret = ret ? ret : ret_ecc;
}
}
return ret;