gpu: nvgpu: change pmu_setup_elpg to return void

MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. In the case of the pmu_setup_elpg operation, all
implementations were always returning 0, so this patch changes the
signature to return void instead.

JIRA NVGPU-3036

Change-Id: I6f0a79314535ba9e3c65d28399b117b058bb23ca
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092680
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c

@@ -98,9 +98,8 @@ static struct pg_init_sequence_list _pginitseq_gm20b[] = {
 		{ 0x0010e040U, 0x00000000U},
 };
 
-int gm20b_pmu_setup_elpg(struct gk20a *g)
+void gm20b_pmu_setup_elpg(struct gk20a *g)
 {
-	int ret = 0;
 	size_t reg_writes;
 	size_t index;
 
@@ -116,7 +115,6 @@ int gm20b_pmu_setup_elpg(struct gk20a *g)
 	}
 
 	nvgpu_log_fn(g, "done");
-	return ret;
 }
 
 void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr)

drivers/gpu/nvgpu/common/pmu/pmu_gm20b.h

@@ -27,7 +27,7 @@
 
 struct gk20a;
 
-int gm20b_pmu_setup_elpg(struct gk20a *g);
+void gm20b_pmu_setup_elpg(struct gk20a *g);
 void pmu_dump_security_fuses_gm20b(struct gk20a *g);
 void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr);
 bool gm20b_pmu_is_debug_mode_en(struct gk20a *g);

drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c

@@ -134,9 +134,8 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = {
 		{0x0010e004U, 0x0000008EU},
 };
 
-int gp10b_pmu_setup_elpg(struct gk20a *g)
+void gp10b_pmu_setup_elpg(struct gk20a *g)
 {
-	int ret = 0;
 	size_t reg_writes;
 	size_t index;
 
@@ -152,7 +151,6 @@ int gp10b_pmu_setup_elpg(struct gk20a *g)
 	}
 
 	nvgpu_log_fn(g, "done");
-	return ret;
 }
 
 void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)

drivers/gpu/nvgpu/common/pmu/pmu_gp10b.h

@@ -30,7 +30,7 @@
 struct gk20a;
 
 bool gp10b_is_pmu_supported(struct gk20a *g);
-int gp10b_pmu_setup_elpg(struct gk20a *g);
+void gp10b_pmu_setup_elpg(struct gk20a *g);
 void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr);
 
 #endif /* NVGPU_PMU_GP10B_H */

drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c

@@ -112,9 +112,8 @@ static struct pg_init_sequence_list _pginitseq_gv11b[] = {
 	{0x00020004U, 0x00000000U} ,
 };
 
-int gv11b_pmu_setup_elpg(struct gk20a *g)
+void gv11b_pmu_setup_elpg(struct gk20a *g)
 {
-	int ret = 0;
 	size_t reg_writes;
 	size_t index;
 
@@ -130,7 +129,6 @@ int gv11b_pmu_setup_elpg(struct gk20a *g)
 	}
 
 	nvgpu_log_fn(g, "done");
-	return ret;
 }
 
 bool gv11b_is_pmu_supported(struct gk20a *g)

drivers/gpu/nvgpu/common/pmu/pmu_gv11b.h

@@ -31,7 +31,7 @@ struct gk20a;
 
 bool gv11b_is_pmu_supported(struct gk20a *g);
 int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu);
-int gv11b_pmu_setup_elpg(struct gk20a *g);
+void gv11b_pmu_setup_elpg(struct gk20a *g);
 u32 gv11b_pmu_get_irqdest(struct gk20a *g);
 void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
 void gv11b_setup_apertures(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1402,7 +1402,7 @@ struct gpu_ops {
 		int (*pmu_perfmon_start_sampling)(struct nvgpu_pmu *pmu);
 		int (*pmu_perfmon_stop_sampling)(struct nvgpu_pmu *pmu);
 		int (*pmu_perfmon_get_samples_rpc)(struct nvgpu_pmu *pmu);
-		int (*pmu_setup_elpg)(struct gk20a *g);
+		void (*pmu_setup_elpg)(struct gk20a *g);
 		u32 (*pmu_get_queue_head)(u32 i);
 		u32 (*pmu_get_queue_head_size)(void);
 		u32 (*pmu_get_queue_tail_size)(void);