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gpu: nvgpu: use u32 for priv_cmd_queue get/put/size

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Switch to a larger integer type for priv_cmd_queue get/put/size
fields.  The previous 16-bit int type overflowed on >= 2048 gpfifo
buffer sizes.  This triggered a div-by-zero kernel panic.

Bug 1592391

Signed-off-by: Janne Hellsten <jhellsten@nvidia.com>
Change-Id: Ibffcbbd145f39fdb4a63d05b1dcb42bb4b101795
Reviewed-on: http://git-master/r/667103
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Janne Hellsten
2014-12-23 11:35:07 +02:00
committed by Dan Willemsen
parent 4f3647ca32
commit 57eeccb4a5
1 changed files with 5 additions and 5 deletions
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10
drivers/gpu/nvgpu/gk20a/mm_gk20a.h
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@@ -223,9 +223,9 @@ struct page_directory_gk20a {
struct priv_cmd_queue {
struct priv_cmd_queue_mem_desc mem;
u64 base_gpuva; /* gpu_va base */
u16 size; /* num of entries in words */
u16 put; /* put for priv cmd queue */
u16 get; /* get for priv cmd queue */
u32 size; /* num of entries in words */
u32 put; /* put for priv cmd queue */
u32 get; /* get for priv cmd queue */
struct list_head free; /* list of pre-allocated free entries */
struct list_head head; /* list of used entries */
};
@@ -233,8 +233,8 @@ struct priv_cmd_queue {
struct priv_cmd_entry {
u32 *ptr;
u64 gva;
u16 get; /* start of entry in queue */
u16 size; /* in words */
u32 get; /* start of entry in queue */
u32 size; /* in words */
u32 gp_get; /* gp_get when submitting last priv cmd */
u32 gp_put; /* gp_put when submitting last priv cmd */
u32 gp_wrap; /* wrap when submitting last priv cmd */