gpu: nvgpu: mc: address code inspection gaps

Address following issues uncovered during inspection:
1. Remove the doxygen comment from nvgpu_wait_for_deferred_interrupts
   definition.
2. Use NVGPU_MC_INTR_STALLING instead of hardcoding the index.
3. Define doxygen groups NVGPU_MC_UNIT_ENUMS,
   NVGPU_MC_INTR_TYPE_DEFINES, NVGPU_MC_INTR_UNIT_DEFINES and
   NVGPU_MC_INTR_ENABLE_DEFINES.
4. Update the doxygen comments.
5. Fix the cleanup, typo in the description of the test
   test_wait_for_deferred_interrupts.

JIRA NVGPU-4795

Change-Id: Ifc6756832aabf9dd42ee174eb1373495e6d38c86
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287627
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/mc/mc.c

@@ -25,14 +25,6 @@
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
 
-/**
- * nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete
- *
- * @g - The GPU to wait on.
- *
- * Waits until all interrupt handlers that have been scheduled to run have
- * completed.
- */
 void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
 {
 	/* wait until all stalling irqs are handled */

drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c

@@ -182,7 +182,7 @@ void mc_gp10b_isr_stall(struct gk20a *g)
 	u32 engine_id = 0U;
 	enum nvgpu_fifo_engine engine_enum;
 
-	mc_intr_0 = nvgpu_readl(g, mc_intr_r(0));
+	mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
 
 	nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0);
 

drivers/gpu/nvgpu/hal/mc/mc_gv100.c

@@ -1,7 +1,7 @@
 /*
  * GV100 master
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -42,7 +42,7 @@ bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
 bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
 			u32 *eng_intr_pending)
 {
-	u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(0));
+	u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
 	u32 stall_intr, eng_intr_mask;
 
 	eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, engine_id);

drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c

@@ -1,7 +1,7 @@
 /*
  * GV11B master
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
 bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
 			u32 *eng_intr_pending)
 {
-	u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(0));
+	u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
 	u32 stall_intr, eng_intr_mask;
 
 	eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, engine_id);

drivers/gpu/nvgpu/include/nvgpu/mc.h

@@ -120,9 +120,15 @@
 struct gk20a;
 
 /**
- * Enumeration of all units intended to be used by any HAL that requires
+ * @defgroup NVGPU_MC_UNIT_ENUMS
- * unit as parameter. Units are added to the enumeration as needed, so
+ *
- * it is not complete.
+ * Enumeration of all units intended to be used by enabling/disabling HAL
+ * that requires unit as parameter. Units are added to the enumeration as
+ * needed, so it is not complete.
+ */
+
+/**
+ * @ingroup NVGPU_MC_UNIT_ENUMS
  */
 enum nvgpu_unit {
 	/** FIFO Engine */
@@ -144,15 +150,39 @@ enum nvgpu_unit {
 /** Bit offset of the Architecture field in the HW version register */
 #define NVGPU_GPU_ARCHITECTURE_SHIFT 4U
 
-/** Index for accessing registers corresponding to stalling interrupts */
+/**
+ * @defgroup NVGPU_MC_INTR_TYPE_DEFINES
+ *
+ * Defines of all MC unit interrupt types.
+ */
+
+/**
+ * @ingroup NVGPU_MC_INTR_TYPE_DEFINES
+ */
+/**
+ * Index for accessing registers corresponding to stalling interrupts.
+ */
 #define NVGPU_MC_INTR_STALLING		0U
-/** Index for accessing registers corresponding to non-stalling interrupts */
+/**
+ * Index for accessing registers corresponding to non-stalling
+ * interrupts.
+ */
 #define NVGPU_MC_INTR_NONSTALLING	1U
 
 /** Operations that will need to be executed on non stall workqueue. */
 #define NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE	BIT32(0)
 #define NVGPU_NONSTALL_OPS_POST_EVENTS		BIT32(1)
 
+/**
+ * @defgroup NVGPU_MC_INTR_UNIT_DEFINES
+ *
+ * Defines of all units intended to be used by any interrupt related
+ * HAL that requires unit as parameter.
+ */
+
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ */
 /** MC interrupt for Bus unit. */
 #define MC_INTR_UNIT_BUS	0
 /** MC interrupt for PRIV_RING unit. */
@@ -174,9 +204,22 @@ enum nvgpu_unit {
 /** MC interrupt for FBPA unit. */
 #define MC_INTR_UNIT_FBPA	9
 
-/** Value to be passed to mc.intr_*_unit_config to enable the interrupt. */
+/**
+ * @defgroup NVGPU_MC_INTR_ENABLE_DEFINES
+ *
+ * Defines for MC unit interrupt enabling/disabling.
+ */
+
+/**
+ * @ingroup NVGPU_MC_INTR_ENABLE_DEFINES
+ * Value to be passed to mc.intr_*_unit_config to enable the interrupt.
+ */
 #define MC_INTR_ENABLE		true
-/** Value to be passed to mc.intr_*_unit_config to disable the interrupt. */
+
+/**
+ * @ingroup NVGPU_MC_INTR_ENABLE_DEFINES
+ * Value to be passed to mc.intr_*_unit_config to disable the interrupt.
+ */
 #define MC_INTR_DISABLE		false
 
 /**
@@ -184,6 +227,7 @@ enum nvgpu_unit {
  * interrupt handling of the units/engines.
  */
 struct nvgpu_mc {
+	/** Lock to access the MC interrupt registers */
 	struct nvgpu_spinlock intr_lock;
 
 	/** Lock to access the mc_enable_r */
@@ -265,7 +309,7 @@ void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
  *
  * @param g [in]	The GPU driver struct.
  *
- * This function is invoked before powering off or finishing
+ * This function is invoked before powering on, powering off or finishing
  * SW quiesce of nvgpu driver.
  *
  * Steps:

userspace/units/mc/nvgpu-mc.c

@@ -784,6 +784,9 @@ int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
 	nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
 	nvgpu_wait_for_deferred_interrupts(g);
 
+	/* disable the fault injection */
+	nvgpu_posix_enable_fault_injection(cond_fi, false, 0);
+
 	return UNIT_SUCCESS;
 }
 

userspace/units/mc/nvgpu-mc.h

@@ -332,7 +332,7 @@ int test_reset_mask(struct unit_module *m, struct gk20a *g, void *args);
 /**
  * Test specification for: test_wait_for_deferred_interrupts
  *
- * Description: Validate functionality of HAL to get reset mask for a unit.
+ * Description: Validate functionality of waiting for deferred interrupts.
  *
  * Test Type: Feature
  *
@@ -351,6 +351,7 @@ int test_reset_mask(struct unit_module *m, struct gk20a *g, void *args);
  * - Call the API.
  * - Set the irq count states in the gk20a struct to simulate pending non-stall
  *   interrupts.
+ * - Disable cond fault injection.
  *
  * Output: Returns PASS if expected result is met, FAIL otherwise.
  */