gpu: nvgpu: add compbit backing size to gr_gk20a

Add compbit_backing_size variable to struct gr_gk20a to hold
compbit backing size
And copy this value in respective init_comptags() HAL

Bug 2180284
Jira NVGPUT-12

Change-Id: I3c1bea3a6b7ed39a1e901357e6e062dbf45b747b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776028
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c

@@ -105,6 +105,7 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 
 	gr->max_comptag_lines = max_comptag_lines;
 	gr->comptags_per_cacheline = comptags_per_cacheline;
+	gr->compbit_backing_size = compbit_backing_size;
 
 	return 0;
 }

drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c

@@ -130,6 +130,7 @@ int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 	gr->max_comptag_lines = max_comptag_lines;
 	gr->comptags_per_cacheline = comptags_per_cacheline;
 	gr->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice;
+	gr->compbit_backing_size = compbit_backing_size;
 
 	return 0;
 }

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -333,6 +333,7 @@ struct gr_gk20a {
 	u32 num_fbps;
 
 	u32 max_comptag_lines;
+	u32 compbit_backing_size;
 	u32 comptags_per_cacheline;
 	u32 slices_per_ltc;
 	u32 cacheline_size;