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gpu: nvgpu: fix MISRA 21.2 violation in io.h

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MISRA Rule 21.2 prohibits naming functions beginning with double
underscore. So, rename __nvgpu_readl() to nvgpu_readl_impl().

JIRA NVGPU-3361

Change-Id: Ia09a0f57e250fa3934f843671a529ee1b2ac2493
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118041
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-05-13 16:06:30 -04:00
committed by mobile promotions
parent 16d98af02b
commit 5a0a711464
7 changed files with 13 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/mc/mc.c
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@@ -30,7 +30,7 @@
u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
{ {
u32 val = __nvgpu_readl(g, mc_boot_0_r()); u32 val = nvgpu_readl_impl(g, mc_boot_0_r());
if (val != U32_MAX) { if (val != U32_MAX) {

4
drivers/gpu/nvgpu/include/nvgpu/io.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -38,7 +38,7 @@ struct gk20a;
void nvgpu_writel(struct gk20a *g, u32 r, u32 v); void nvgpu_writel(struct gk20a *g, u32 r, u32 v);
void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v); void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v);
u32 nvgpu_readl(struct gk20a *g, u32 r); u32 nvgpu_readl(struct gk20a *g, u32 r);
u32 __nvgpu_readl(struct gk20a *g, u32 r); u32 nvgpu_readl_impl(struct gk20a *g, u32 r);
void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v); void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v);
void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v); void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v);
void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v); void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v);

2
drivers/gpu/nvgpu/libnvgpu-drv.export
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@@ -2,7 +2,6 @@
__nvgpu_log_dbg __nvgpu_log_dbg
__nvgpu_log_msg __nvgpu_log_msg
__nvgpu_readl
bitmap_clear bitmap_clear
bitmap_find_next_zero_area_off bitmap_find_next_zero_area_off
bitmap_set bitmap_set
@@ -154,6 +153,7 @@ nvgpu_rbtree_range_search
nvgpu_rbtree_search nvgpu_rbtree_search
nvgpu_rbtree_unlink nvgpu_rbtree_unlink
nvgpu_readl nvgpu_readl
nvgpu_readl_impl
nvgpu_runlist_construct_locked nvgpu_runlist_construct_locked
nvgpu_rwsem_init nvgpu_rwsem_init
nvgpu_tsg_default_timeslice_us nvgpu_tsg_default_timeslice_us

4
drivers/gpu/nvgpu/os/linux/linux-io.c
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@@ -45,7 +45,7 @@ void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v)
u32 nvgpu_readl(struct gk20a *g, u32 r) u32 nvgpu_readl(struct gk20a *g, u32 r)
{ {
u32 v = __nvgpu_readl(g, r); u32 v = nvgpu_readl_impl(g, r);
if (v == 0xffffffff) if (v == 0xffffffff)
nvgpu_check_gpu_state(g); nvgpu_check_gpu_state(g);
@@ -53,7 +53,7 @@ u32 nvgpu_readl(struct gk20a *g, u32 r)
return v; return v;
} }
u32 __nvgpu_readl(struct gk20a *g, u32 r) u32 nvgpu_readl_impl(struct gk20a *g, u32 r)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
u32 v = 0xffffffff; u32 v = 0xffffffff;

4
drivers/gpu/nvgpu/os/posix/posix-io.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -94,7 +94,7 @@ void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
BUG(); BUG();
} }
u32 __nvgpu_readl(struct gk20a *g, u32 r) u32 nvgpu_readl_impl(struct gk20a *g, u32 r)
{ {
struct nvgpu_posix_io_callbacks *callbacks = struct nvgpu_posix_io_callbacks *callbacks =
nvgpu_os_posix_from_gk20a(g)->callbacks; nvgpu_os_posix_from_gk20a(g)->callbacks;

2
userspace/required_tests.json
View File

@@ -1423,7 +1423,7 @@
"unit": "posix_env" "unit": "posix_env"
}, },
{ {
"test": "__readl", "test": "readl_impl",
"test_level": 0, "test_level": 0,
"unit": "posix_mockio" "unit": "posix_mockio"
}, },

8
userspace/units/posix/mockio/posix-mockio.c
View File

@@ -191,9 +191,9 @@ struct readl_test_args nvgpu_readl_args = {
.fn = nvgpu_readl .fn = nvgpu_readl
}; };
struct readl_test_args __nvgpu_readl_args = { struct readl_test_args nvgpu_readl_impl_args = {
.name = "__nvgpu_readl", .name = "nvgpu_readl_impl",
.fn = __nvgpu_readl .fn = nvgpu_readl_impl
}; };
struct readl_test_args nvgpu_bar1_readl_args = { struct readl_test_args nvgpu_bar1_readl_args = {
@@ -333,7 +333,7 @@ struct unit_module_test posix_mockio_tests[] = {
UNIT_TEST(usermode_writel, test_writel, UNIT_TEST(usermode_writel, test_writel,
&nvgpu_usermode_writel_args, 0), &nvgpu_usermode_writel_args, 0),
UNIT_TEST(readl, test_readl, &nvgpu_readl_args, 0), UNIT_TEST(readl, test_readl, &nvgpu_readl_args, 0),
UNIT_TEST(__readl, test_readl, &__nvgpu_readl_args, 0), UNIT_TEST(readl_impl, test_readl, &nvgpu_readl_impl_args, 0),
UNIT_TEST(bar1_readl, test_readl, &nvgpu_bar1_readl_args, 0), UNIT_TEST(bar1_readl, test_readl, &nvgpu_bar1_readl_args, 0),
UNIT_TEST(test_register_space, test_register_space, NULL, 0), UNIT_TEST(test_register_space, test_register_space, NULL, 0),
}; };