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gpu: nvgpu: add reset_method pbdma gops

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Add reset_method hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ice9c3f6aea33a8dadae5841f1a6387303495ba98
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854547
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2023-02-07 17:21:27 +00:00
committed by mobile promotions
parent 30727e8a93
commit 5aae7df6cd
4 changed files with 7 additions and 4 deletions
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7
drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c
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@@ -444,12 +444,12 @@ static bool ga10b_pbdma_handle_intr_0_legacy(struct gk20a *g, u32 pbdma_id,
if ((pbdma_intr_0 & pbdma_intr_0_pbentry_pending_f()) != 0U) { if ((pbdma_intr_0 & pbdma_intr_0_pbentry_pending_f()) != 0U) {
g->ops.pbdma.reset_header(g, pbdma_id); g->ops.pbdma.reset_header(g, pbdma_id);
ga10b_pbdma_reset_method(g, pbdma_id, 0); g->ops.pbdma.reset_method(g, pbdma_id, 0);
recover = true; recover = true;
} }
if ((pbdma_intr_0 & pbdma_intr_0_method_pending_f()) != 0U) { if ((pbdma_intr_0 & pbdma_intr_0_method_pending_f()) != 0U) {
ga10b_pbdma_reset_method(g, pbdma_id, 0); g->ops.pbdma.reset_method(g, pbdma_id, 0);
recover = true; recover = true;
} }
@@ -465,8 +465,7 @@ static bool ga10b_pbdma_handle_intr_0_legacy(struct gk20a *g, u32 pbdma_id,
for (i = 0U; i < 4U; i++) { for (i = 0U; i < 4U; i++) {
if (g->ops.pbdma.is_sw_method_subch(g, if (g->ops.pbdma.is_sw_method_subch(g,
pbdma_id, i)) { pbdma_id, i)) {
ga10b_pbdma_reset_method(g, g->ops.pbdma.reset_method(g, pbdma_id, i);
pbdma_id, i);
} }
} }
recover = true; recover = true;

1
drivers/gpu/nvgpu/hal/init/hal_ga100.c
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@@ -1061,6 +1061,7 @@ static const struct gops_pbdma ga100_ops_pbdma = {
.set_clear_intr_offsets = ga100_pbdma_set_clear_intr_offsets, .set_clear_intr_offsets = ga100_pbdma_set_clear_intr_offsets,
.read_data = ga100_pbdma_read_data, .read_data = ga100_pbdma_read_data,
.reset_header = ga10b_pbdma_reset_header, .reset_header = ga10b_pbdma_reset_header,
.reset_method = ga10b_pbdma_reset_method,
.device_fatal_0_intr_descs = ga10b_pbdma_device_fatal_0_intr_descs, .device_fatal_0_intr_descs = ga10b_pbdma_device_fatal_0_intr_descs,
.channel_fatal_0_intr_descs = ga10b_pbdma_channel_fatal_0_intr_descs, .channel_fatal_0_intr_descs = ga10b_pbdma_channel_fatal_0_intr_descs,
.restartable_0_intr_descs = gm20b_pbdma_restartable_0_intr_descs, .restartable_0_intr_descs = gm20b_pbdma_restartable_0_intr_descs,

1
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
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@@ -1079,6 +1079,7 @@ static const struct gops_pbdma ga10b_ops_pbdma = {
.set_clear_intr_offsets = ga10b_pbdma_set_clear_intr_offsets, .set_clear_intr_offsets = ga10b_pbdma_set_clear_intr_offsets,
.read_data = ga10b_pbdma_read_data, .read_data = ga10b_pbdma_read_data,
.reset_header = ga10b_pbdma_reset_header, .reset_header = ga10b_pbdma_reset_header,
.reset_method = ga10b_pbdma_reset_method,
.device_fatal_0_intr_descs = ga10b_pbdma_device_fatal_0_intr_descs, .device_fatal_0_intr_descs = ga10b_pbdma_device_fatal_0_intr_descs,
.channel_fatal_0_intr_descs = ga10b_pbdma_channel_fatal_0_intr_descs, .channel_fatal_0_intr_descs = ga10b_pbdma_channel_fatal_0_intr_descs,
.restartable_0_intr_descs = gm20b_pbdma_restartable_0_intr_descs, .restartable_0_intr_descs = gm20b_pbdma_restartable_0_intr_descs,

2
drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
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@@ -64,6 +64,8 @@ struct gops_pbdma {
u32 (*acquire_val)(u64 timeout); u32 (*acquire_val)(u64 timeout);
u32 (*read_data)(struct gk20a *g, u32 pbdma_id); u32 (*read_data)(struct gk20a *g, u32 pbdma_id);
void (*reset_header)(struct gk20a *g, u32 pbdma_id); void (*reset_header)(struct gk20a *g, u32 pbdma_id);
void (*reset_method)(struct gk20a *g, u32 pbdma_id,
u32 pbdma_method_index);
u32 (*device_fatal_0_intr_descs)(void); u32 (*device_fatal_0_intr_descs)(void);
u32 (*channel_fatal_0_intr_descs)(void); u32 (*channel_fatal_0_intr_descs)(void);
u32 (*restartable_0_intr_descs)(void); u32 (*restartable_0_intr_descs)(void);