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gpu: nvgpu: pmu: fix MISRA 10.3 violations

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MISRA Rule 10.3 prohibits assignment of objects of different essential
or narrower type. This fixes a number of MISRA 10.3 violations in the
common/pmu unit.

JIRA: NVGPU-3023

Change-Id: Ib424326887a2810b708e35cc350cd27919a2d15d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084204
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-03-28 14:20:55 -04:00
committed by mobile promotions
parent aa8cef278e
commit 5be9fba5af
2 changed files with 16 additions and 5 deletions
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6
drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
View File

@@ -598,7 +598,8 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g)
(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
cmd.hdr.unit_id = PMU_UNIT_PG;
cmd.hdr.size = PMU_CMD_HDR_SIZE +
nvgpu_assert(PMU_CMD_HDR_SIZE < U32(U8_MAX));
cmd.hdr.size = U8(PMU_CMD_HDR_SIZE) +
g->ops.pmu_ver.pg_cmd_eng_buf_load_size(&cmd.cmd.pg);
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type(&cmd.cmd.pg,
PMU_PG_CMD_ID_ENG_BUF_LOAD);
@@ -639,7 +640,8 @@ void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g)
(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
cmd.hdr.unit_id = PMU_UNIT_PG;
cmd.hdr.size = PMU_CMD_HDR_SIZE +
nvgpu_assert(PMU_CMD_HDR_SIZE < U32(U8_MAX));
cmd.hdr.size = U8(PMU_CMD_HDR_SIZE) +
g->ops.pmu_ver.pg_cmd_eng_buf_load_size(&cmd.cmd.pg);
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type(&cmd.cmd.pg,
PMU_PG_CMD_ID_ENG_BUF_LOAD);

15
drivers/gpu/nvgpu/common/pmu/pmu_fw.c
View File

@@ -993,17 +993,26 @@ static void *get_pmu_sequence_out_alloc_ptr_v1(struct pmu_sequence *seq)
static u8 pg_cmd_eng_buf_load_size_v0(struct pmu_pg_cmd *pg)
{
return (u32)sizeof(pg->eng_buf_load_v0);
size_t tmp_size = sizeof(pg->eng_buf_load_v0);
nvgpu_assert(tmp_size <= (size_t)U8_MAX);
return U8(tmp_size);
}
static u8 pg_cmd_eng_buf_load_size_v1(struct pmu_pg_cmd *pg)
{
return (u32)sizeof(pg->eng_buf_load_v1);
size_t tmp_size = sizeof(pg->eng_buf_load_v1);
nvgpu_assert(tmp_size <= (size_t)U8_MAX);
return U8(tmp_size);
}
static u8 pg_cmd_eng_buf_load_size_v2(struct pmu_pg_cmd *pg)
{
return (u32)sizeof(pg->eng_buf_load_v2);
size_t tmp_size = sizeof(pg->eng_buf_load_v2);
nvgpu_assert(tmp_size <= (size_t)U8_MAX);
return U8(tmp_size);
}
static void pg_cmd_eng_buf_load_set_cmd_type_v0(struct pmu_pg_cmd *pg,