nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: make fifo/ch functions called by RM Server global

Browse Source 
The patch declares globally few channel/fifo HAL functions
required for QNX code compilation (as they are being referred
elsewhere in QNX code). This is required as a part of
bringing in the nvgpu Channel/FIFO HAL into QNX.

Jira VQRM-3058

Change-Id: Ia176535b64de981d2f7ddb20f62015a0da74fd2a
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1662411
GVS: Gerrit_Virtual_Submit
Tested-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sourab Gupta
2017-12-27 14:24:11 +05:30
committed by mobile promotions
parent aa7ee8dac0
commit 5c27ac91fd
4 changed files with 19 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gk20a/channel_gk20a.c
View File

@@ -256,7 +256,7 @@ void gk20a_disable_channel(struct channel_gk20a *ch)
channel_gk20a_update_runlist(ch, false);
}
static void gk20a_wait_until_counter_is_N(
void gk20a_wait_until_counter_is_N(
struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value,
struct nvgpu_cond *c, const char *caller, const char *counter_name)
{

3
drivers/gpu/nvgpu/gk20a/channel_gk20a.h
View File

@@ -340,6 +340,9 @@ int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g,
unsigned int timeslice_period,
unsigned int *__timeslice_timeout, unsigned int *__timeslice_scale);
void gk20a_wait_until_counter_is_N(
struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value,
struct nvgpu_cond *c, const char *caller, const char *counter_name);
int channel_gk20a_alloc_job(struct channel_gk20a *c,
struct channel_gk20a_job **job_out);
void channel_gk20a_free_job(struct channel_gk20a *c,

8
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -862,7 +862,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
return 0;
}
static int gk20a_init_fifo_setup_sw(struct gk20a *g)
int gk20a_init_fifo_setup_sw(struct gk20a *g)
{
struct fifo_gk20a *f = &g->fifo;
unsigned int chid, i;
@@ -2093,7 +2093,7 @@ u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g,
return active_engine_id;
}
static bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch,
bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch,
bool *verbose, u32 *ms)
{
bool recover = false;
@@ -2971,7 +2971,7 @@ static void gk20a_fifo_runlist_reset_engines(struct gk20a *g, u32 runlist_id)
gk20a_fifo_recover(g, engines, ~(u32)0, false, false, true);
}
static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
{
struct nvgpu_timeout timeout;
unsigned long delay = GR_IDLE_CHECK_DEFAULT;
@@ -3032,7 +3032,7 @@ void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist)
}
/* recursively construct a runlist with interleaved bare channels and TSGs */
static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
struct fifo_runlist_info_gk20a *runlist,
u32 cur_level,
u32 *runlist_entry,

11
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -378,6 +378,15 @@ int gk20a_fifo_setup_userd(struct channel_gk20a *c);
u32 gk20a_fifo_pbdma_acquire_val(u64 timeout);
u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
struct fifo_runlist_info_gk20a *runlist,
u32 cur_level,
u32 *runlist_entry,
bool interleave_enabled,
bool prev_empty,
u32 *entries_left);
int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id);
int gk20a_init_fifo_setup_sw(struct gk20a *g);
void gk20a_fifo_handle_runlist_event(struct gk20a *g);
bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
u32 engine_subid, bool fake_fault);
@@ -386,6 +395,8 @@ void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids,
u32 hw_id, unsigned int id_type, unsigned int rc_type,
struct mmu_fault_info *mmfault);
bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch,
bool *verbose, u32 *ms);
bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
bool *verbose, u32 *ms);
bool gk20a_fifo_handle_sched_error(struct gk20a *g);