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gpu: nvgpu: gr_priv header include cleanup

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Add more apis in gr_utils for accessing variables within gr struct.
This helps to avoid including gr_priv.h outside gr files and
derefencing gr struct.

Jira NVGPU-3218

Change-Id: I6f24cc302f10aa1da14a981d80c400a027c9a115
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115930
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-05-09 14:32:05 -07:00
committed by mobile promotions
parent e615e8f0ff
commit 5c60645cfa
17 changed files with 155 additions and 62 deletions
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13
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -38,6 +38,7 @@
#include <nvgpu/gr/zbc.h>
#include <nvgpu/gr/zcull.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_utils.h>
#include <nvgpu/gr/warpstate.h>
#include <nvgpu/channel.h>
#include <nvgpu/pmu/pmgr.h>
@@ -45,8 +46,6 @@
#include <nvgpu/fence.h>
#include <nvgpu/channel_sync_syncpt.h>
#include "common/gr/gr_priv.h"
#include "ioctl_ctrl.h"
#include "ioctl_dbg.h"
#include "ioctl_as.h"
@@ -1667,6 +1666,8 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
struct nvgpu_gr_zbc_entry *zbc_val;
struct nvgpu_gr_zbc_query_params *zbc_tbl;
struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
struct nvgpu_gr_zcull *gr_zcull = nvgpu_gr_get_zcull_ptr(g);
struct nvgpu_gr_zbc *gr_zbc = nvgpu_gr_get_zbc_ptr(g);
int err = 0;
u32 i;
@@ -1697,7 +1698,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
case NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE:
get_ctx_size_args = (struct nvgpu_gpu_zcull_get_ctx_size_args *)buf;
get_ctx_size_args->size = nvgpu_gr_get_ctxsw_zcull_size(g, g->gr->zcull);
get_ctx_size_args->size = nvgpu_gr_get_ctxsw_zcull_size(g, gr_zcull);
break;
case NVGPU_GPU_IOCTL_ZCULL_GET_INFO:
@@ -1711,7 +1712,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
return -ENOMEM;
err = g->ops.gr.zcull.get_zcull_info(g, gr_config,
g->gr->zcull, zcull_info);
gr_zcull, zcull_info);
if (err) {
nvgpu_kfree(g, zcull_info);
break;
@@ -1762,7 +1763,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
if (!err) {
err = gk20a_busy(g);
if (!err) {
err = g->ops.gr.zbc.set_table(g, g->gr->zbc,
err = g->ops.gr.zbc.set_table(g, gr_zbc,
zbc_val);
gk20a_idle(g);
}
@@ -1781,7 +1782,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
zbc_tbl->type = query_table_args->type;
zbc_tbl->index_size = query_table_args->index_size;
err = g->ops.gr.zbc.query_table(g, g->gr->zbc, zbc_tbl);
err = g->ops.gr.zbc.query_table(g, gr_zbc, zbc_tbl);
if (!err) {
switch (zbc_tbl->type) {

1
drivers/gpu/nvgpu/os/linux/ioctl_tsg.c
View File

@@ -28,6 +28,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_utils.h>
#include <nvgpu/channel.h>
#include <nvgpu/tsg.h>
#include <nvgpu/fifo.h>

1
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -50,6 +50,7 @@
#include <nvgpu/engines.h>
#include <nvgpu/channel.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_utils.h>
#include <nvgpu/pmu/pmu_pstate.h>
#include <nvgpu/cyclestats_snapshot.h>

22
drivers/gpu/nvgpu/os/linux/sysfs.c
View File

@@ -27,13 +27,12 @@
#include <nvgpu/gr/obj_ctx.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_utils.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/pmu/pmu_perfmon.h>
#include <nvgpu/pmu/fw.h>
#include "common/gr/gr_priv.h"
#include "os_linux.h"
#include "sysfs.h"
#include "platform_gk20a.h"
@@ -828,8 +827,9 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct gk20a *g = get_gk20a(dev);
struct nvgpu_gr *gr = g->gr;
unsigned long val = 0;
struct nvgpu_gr_obj_ctx_golden_image *gr_golden_image =
nvgpu_gr_get_golden_image_ptr(g);
nvgpu_mutex_acquire(&g->tpc_pg_lock);
@@ -849,7 +849,7 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
goto exit;
}
if (nvgpu_gr_obj_ctx_get_golden_image_size(gr->golden_image) != 0) {
if (nvgpu_gr_obj_ctx_get_golden_image_size(gr_golden_image) != 0) {
nvgpu_err(g, "golden image size already initialized");
nvgpu_mutex_release(&g->tpc_pg_lock);
return -ENODEV;
@@ -875,6 +875,10 @@ static ssize_t tpc_fs_mask_store(struct device *dev,
{
struct gk20a *g = get_gk20a(dev);
struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
struct nvgpu_gr_obj_ctx_golden_image *gr_golden_image =
nvgpu_gr_get_golden_image_ptr(g);
struct nvgpu_gr_falcon *gr_falcon =
nvgpu_gr_get_falcon_ptr(g);
unsigned long val = 0;
if (kstrtoul(buf, 10, &val) < 0)
@@ -890,12 +894,12 @@ static ssize_t tpc_fs_mask_store(struct device *dev,
g->ops.gr.set_gpc_tpc_mask(g, 0);
nvgpu_gr_obj_ctx_set_golden_image_size(g->gr->golden_image, 0);
nvgpu_gr_obj_ctx_deinit(g, g->gr->golden_image);
g->gr->golden_image = NULL;
nvgpu_gr_obj_ctx_set_golden_image_size(gr_golden_image, 0);
nvgpu_gr_obj_ctx_deinit(g, gr_golden_image);
nvgpu_gr_reset_golden_image_ptr(g);
nvgpu_gr_falcon_remove_support(g, g->gr->falcon);
g->gr->falcon = NULL;
nvgpu_gr_falcon_remove_support(g, gr_falcon);
nvgpu_gr_reset_falcon_ptr(g);
nvgpu_gr_config_deinit(g, gr_config);
/* Cause next poweron to reinit just gr */