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gpu: nvgpu: gr/init MISRA fixes for Rule 10.3

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Fix MISRA violations for Rule 10.3 in gr.init unit
Implicit conversion from essential type "unsigned 64-bit int"
to different or narrower essential type "unsigned 32-bit int"

Jira NVGPU-3389

Change-Id: I00bc876f271242a513371477c781e78b2ee42b6a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116733
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-05-10 11:50:52 -07:00
committed by mobile promotions
parent e332b6023c
commit e615e8f0ff
2 changed files with 10 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
View File

@@ -919,6 +919,7 @@ void gm20b_gr_init_commit_global_pagepool(struct gk20a *g,
bool global_ctx)
{
u32 pp_addr;
u32 pp_size;
addr = addr >> gr_scc_pagepool_base_addr_39_8_align_bits_v();
@@ -935,25 +936,26 @@ void gm20b_gr_init_commit_global_pagepool(struct gk20a *g,
addr, size);
pp_addr = (u32)addr;
pp_size = (u32)size;
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_pagepool_base_r(),
gr_scc_pagepool_base_addr_39_8_f(pp_addr), patch);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_pagepool_r(),
gr_scc_pagepool_total_pages_f(size) |
gr_scc_pagepool_total_pages_f(pp_size) |
gr_scc_pagepool_valid_true_f(), patch);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_gcc_pagepool_base_r(),
gr_gpcs_gcc_pagepool_base_addr_39_8_f(pp_addr), patch);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_gcc_pagepool_r(),
gr_gpcs_gcc_pagepool_total_pages_f(size), patch);
gr_gpcs_gcc_pagepool_total_pages_f(pp_size), patch);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pd_pagepool_r(),
gr_pd_pagepool_total_pages_f(size) |
gr_pd_pagepool_total_pages_f(pp_size) |
gr_pd_pagepool_valid_true_f(), patch);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_swdx_rm_pagepool_r(),
gr_gpcs_swdx_rm_pagepool_total_pages_f(size) |
gr_gpcs_swdx_rm_pagepool_total_pages_f(pp_size) |
gr_gpcs_swdx_rm_pagepool_valid_true_f(), patch);
}

6
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
View File

@@ -352,6 +352,7 @@ void gp10b_gr_init_commit_global_pagepool(struct gk20a *g,
bool global_ctx)
{
u32 pp_addr;
u32 pp_size;
addr = addr >> gr_scc_pagepool_base_addr_39_8_align_bits_v();
@@ -368,18 +369,19 @@ void gp10b_gr_init_commit_global_pagepool(struct gk20a *g,
addr, size);
pp_addr = (u32)addr;
pp_size = (u32)size;
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_pagepool_base_r(),
gr_scc_pagepool_base_addr_39_8_f(pp_addr), patch);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_pagepool_r(),
gr_scc_pagepool_total_pages_f(size) |
gr_scc_pagepool_total_pages_f(pp_size) |
gr_scc_pagepool_valid_true_f(), patch);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_gcc_pagepool_base_r(),
gr_gpcs_gcc_pagepool_base_addr_39_8_f(pp_addr), patch);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_gcc_pagepool_r(),
gr_gpcs_gcc_pagepool_total_pages_f(size), patch);
gr_gpcs_gcc_pagepool_total_pages_f(pp_size), patch);
}
void gp10b_gr_init_commit_global_attrib_cb(struct gk20a *g,