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gpu: nvgpu: update PLC enabled flag name

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Modify NVGPU_SUPPORT_PLC enabled flag name to
NVGPU_SUPPORT_POST_L2_COMPRESSION keep name more specific.

JIRA NVGPU-4666

Change-Id: I69336d74210457025921149768cfef036891bf72
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2361157
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2020-06-15 10:24:54 -07:00
committed by Alex Waterman
parent fb1433811c
commit 5c7b73e6ca
3 changed files with 4 additions and 4 deletions
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2
drivers/gpu/nvgpu/include/nvgpu/enabled.h
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@@ -259,7 +259,7 @@ struct gk20a;
#define NVGPU_SUPPORT_SM_TTU 88U #define NVGPU_SUPPORT_SM_TTU 88U
/** PLC Compression */ /** PLC Compression */
#define NVGPU_SUPPORT_PLC 89U #define NVGPU_SUPPORT_POST_L2_COMPRESSION 89U
/* /*
* Must be greater than the largest bit offset in the above list. * Must be greater than the largest bit offset in the above list.

4
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
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@@ -255,8 +255,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
NVGPU_SUPPORT_COMPRESSION}, NVGPU_SUPPORT_COMPRESSION},
{NVGPU_GPU_FLAGS_SUPPORT_SM_TTU, {NVGPU_GPU_FLAGS_SUPPORT_SM_TTU,
NVGPU_SUPPORT_SM_TTU}, NVGPU_SUPPORT_SM_TTU},
{NVGPU_GPU_FLAGS_SUPPORT_PLC, {NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION,
NVGPU_SUPPORT_PLC} NVGPU_SUPPORT_POST_L2_COMPRESSION}
}; };
static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)

2
include/uapi/linux/nvgpu.h
View File

@@ -178,7 +178,7 @@ struct nvgpu_gpu_zbc_query_table_args {
/* SM TTU is enabled */ /* SM TTU is enabled */
#define NVGPU_GPU_FLAGS_SUPPORT_SM_TTU (1ULL << 37) #define NVGPU_GPU_FLAGS_SUPPORT_SM_TTU (1ULL << 37)
/* Compression PLC is enabled */ /* Compression PLC is enabled */
#define NVGPU_GPU_FLAGS_SUPPORT_PLC (1ULL << 38) #define NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION (1ULL << 38)
/* SM LRF ECC is enabled */ /* SM LRF ECC is enabled */
#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
/* SM SHM ECC is enabled */ /* SM SHM ECC is enabled */