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gpu: nvgpu: halt gr pipe & gr_reset do not work on fmodel
Do not halt gr pipe as it will hang simulator. Also during ch/tsg teardown, gr_reset without halting gr pipe crashes simulator. Bug 1958308 Change-Id: I4036b4a4999932f05a0f292d4fc51de21d3a030a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566575 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1237,16 +1237,21 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
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if (g->ops.fecs_trace.reset)
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g->ops.fecs_trace.reset(g);
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#endif
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/* HALT_PIPELINE method, halt GR engine. */
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if (gr_gk20a_halt_pipe(g))
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nvgpu_err(g, "failed to HALT gr pipe");
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/*
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* Resetting engine using mc_enable_r() is not enough; we must
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* do full init sequence.
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*/
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gk20a_gr_reset(g);
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if (!nvgpu_platform_is_simulation(g)) {
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/*HALT_PIPELINE method, halt GR engine*/
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if (gr_gk20a_halt_pipe(g))
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nvgpu_err(g, "failed to HALT gr pipe");
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/*
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* resetting engine using mc_enable_r() is not
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* enough, we do full init sequence
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*/
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nvgpu_log(g, gpu_dbg_info, "resetting gr engine");
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gk20a_gr_reset(g);
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} else {
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nvgpu_log(g, gpu_dbg_info,
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"HALT gr pipe not supported and "
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"gr cannot be reset without halting gr pipe");
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}
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if (g->support_pmu && g->can_elpg)
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nvgpu_pmu_enable_elpg(g);
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}
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